generate a 20 MHZ clock(pulse) with duty cycle other than 50

[MegaPowerStar]

Hi friends
is there any way to generate a 20 MHZ clock(pulse) with duty cycle
other than 50 % from master clock 40 MHZ having 50 % duty cycle. this
one should be achieved with out using the PLL function of FPGA
(can be in either verilog/vhdl)

is there any way


please respond as soon as possible

thanx in adv.
regards
MPS

 

[Uwe Bonnes]

MegaPowerStar <dsredy3@mailcity.com> wrote:
: Hi friends
: is there any way to generate a 20 MHZ clock(pulse) with duty cycle
: other than 50 % from master clock 40 MHZ having 50 % duty cycle. this
: one should be achieved with out using the PLL function of FPGA
: (can be in either verilog/vhdl)

: is there any way


: please respond as soon as possible

You can get 25% and 75 % duty cycle
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Prasanna]

Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<bhqd6u$trd$1@news.tu-darmstadt.de>...

MegaPowerStar <dsredy3@mailcity.com> wrote:
: Hi friends
: is there any way to generate a 20 MHZ clock(pulse) with duty cycle
: other than 50 % from master clock 40 MHZ having 50 % duty cycle. this
: one should be achieved with out using the PLL function of FPGA
: (can be in either verilog/vhdl)

: is there any way


: please respond as soon as possible

You can get 25% and 75 % duty cycle

Hi,

Use posedge and negedge 'T' flops and "AND" their outputs.

Helps ?

Regards,

- Prasanna