GDS2 LVS DRC

[rsk]

Hi Friends,
This GDS2 is the final output of the backend which will be given to
FAB.

But whats its abbreviation?(like SDF is standard delay format)

LVS:what are all the Test vectors for this Layout vs schematic?

Different types of IC testing?

DRC:Means Design rule check ,but what kind of rules they are ?

I will be waiting for ur reply.


THANKS IN ADVANCE .


BYE FRIENDS
ravi...

 

[ka]

On Wed, 19 May 2004 14:26:30 -0400, "rsk" <krs_1980@yahoo.co.in>
wrote:

Hi Friends,
This GDS2 is the final output of the backend which will be given to
FAB.

But whats its abbreviation?(like SDF is standard delay format)

Probably Generalized Data Stream but not sure about this.

LVS:what are all the Test vectors for this Layout vs schematic?

for LVS there are no test vectors. For LVS, you first extract the
netlist from the layout by recognizing the devices and the
connectivity and then match the same to the netlist you obtain from
the schematic. It is a deterministic, (mostly) one to one matching.

Different types of IC testing?

DRC:Means Design rule check ,but what kind of rules they are ?

These are generally rules which govern the device generation and

geometry size rules, ie. minimum gate size, poly to well distance,
minimum metal width, metal to metal distance, clearence rules, overlap
rules etc.

 

[Stefan Frank]

On 05/20/2004 04:41 AM, kal wrote:

This GDS2 is the final output of the backend which will be given to
FAB.

But whats its abbreviation?(like SDF is standard delay format)

Probably Generalized Data Stream but not sure about this.

Graphic Design System II

See
<http://okaye.esmartweb.com/gdsii/gdsii.html>

Bye,
Steff