gated clock

hi,

I have a design with two clock that I want to mux toward a single
clock like this

with mode select CLK <=
CLK_1 when mode_1,
CLK_2 when mode_2,
CLK_1 when others;

Is there another manner to do this because Quartus says that CLK is a
gated clock !

thanks

 

[Mike Treseler]

patrick.melet@dmradiocom.fr wrote:

I have a design with two clock that I want to mux toward a single
clock like this

with mode select CLK <=
CLK_1 when mode_1,
CLK_2 when mode_2,
CLK_1 when others;

Is there another manner to do this because Quartus says that CLK is a
gated clock !

http://groups.google.com/groups/search?q=fpga+%22gated+clock%22