gate sizing and interconnect delay

[mahalingamv@gmail.com]

hi all,

why do most of the papers ignore interconnect delay when
optimizing power/delay during gate sizing problem.

is it something we can safely ignore even in circuits < 100 nm.

thanks for the clarification.

regards,
Mali

 

[Colin Paul Gloster]

Mali <mahalingamv@gmail.com> posted on Tue, 05 Jun 2007 20:22:53 -0700:
"why do most of the papers ignore interconnect delay when
optimizing power/delay during gate sizing problem.

is it something we can safely ignore even in circuits < 100 nm."

Hello,

You are insightful. Wires' delays are more significant than gates'
delays for gates whose feature sizes are even as large as
approximately 180 nanometers.

I do not know which papers you were checking. Check papers with the
term "Network on Chip" and you should find papers which contain
mentions of this.

Regards,
Colin Paul Gloster

 

[mahalingamv@gmail.com]

On Jun 12, 7:48 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org>
wrote:

Mali <mahaling...@gmail.com> posted on Tue, 05 Jun 2007 20:22:53 -0700:
"why do most of the papers ignore interconnect delay when
optimizing power/delay during gate sizing problem.

is it something we can safely ignore even in circuits < 100 nm."

Hello,

You are insightful. Wires' delays are more significant than gates'
delays for gates whose feature sizes are even as large as
approximately 180 nanometers.

I do not know which papers you were checking. Check papers with the
term "Network on Chip" and you should find papers which contain
mentions of this.

Regards,
Colin Paul Gloster

hi colin,

thanks for your reply.

you are right when u consider papers on network on chip its defnitely
more
dominating that gate delay. even in design automation problems like
placement
buffer insertion wire delays have to be considered.

however when i see gate sizing" defined as increasing drive strengths
of gates"
wire delay is usually ignored. u can check google or ieeexplore by
just typing
the term "gate sizing" in the search.

some refererences i have are here:

@Inproceedings{ vrudhula1,
author = "{S. Bhardwaj, Y. Cao and S. Vrudhula}",
title = "{Statistical leakage minimization through joint selection
of gate sizes, gate lengths and threshold voltage}",
booktitle ="{ASP-DAC}",
Pages ={24-27},
year = {2006},
}

@Inproceedings{ zhou1,
author = "{D. Sinha, N.V. Shenoy and H. Zhou}",
title = "{Statistical Timing Yield Optimization by Gate Sizing}",
booktitle ="{IEEE Trans. on VLSI Systems}",
Pages ={1140-1146},
year = {2006},
}
@Inproceedings{ sarrafzadeh,
author = "{C. Chen and M. Sarrafzadeh }",
title = "{Simultaneous voltage scaling and gate sizing for low-power
design}",
booktitle ="{IEEE Trans. on Circuits and Systems}",
Pages ={400-408},
year = {2002},
}

@Inproceedings{ coudert,
author = "{O. Coudert }",
title = "{Gate sizing for constrained delay/power/area
optimization}",
booktitle ="{IEEE Trans. on VLSI Systems}",
Pages ={465-472},
year = {1997},
}


@inproceedings{mani_iccd,
author = "{M. Mani and M. Orshansky}",
title = "{A New Statistical Optimization Algorithm for Gate
Sizing}",
booktitle = {International Conference on Computer Design},
pages = {272-277},
year = {2004}
}

@inproceedings{ashok,
author = {Murugavel, A. K and Ranganathan, N.},
title = "{Gate Sizing and Buffer Insertion using Economic models for
Power Optimization}",
booktitle = {International conference on VLSI Design},
year = {2004},
pages = {195-200},
}




@inproceedings{hashimoto,
AUTHOR = "{M. Hashimoto and H. Onodera}",
TITLE = "{A Performance Optimization Method by Gate Sizing using
Statistical Static Timing Analysis}",
booktitle = {International Symposium on Physical Design},
PAGES = {111-116},
YEAR = {2000}}


thanks again for replying.

regards,
Mahalingam