P
Peter Gavin
Guest
Hi everyone,
I hope someone here can help me The group at my university
received licenses from Synopsys for their suite of tools, and a few of
us students have been given the task of trying to figure out how to
use them. Unfortunately, no one here has any prior experience with
them, and the documentation that comes with it is quite terse and
doesn't explain some of the finer details.
In any case, we've designed a very simple CPU model in verilog, and
we've been successful in doing a behavioral simulation with VCS. So I
figured I'd try doing a gate-level simulation next, because after that
I want to do power usage analysis on the design.
So in any case, we wrote this script to do the synthesis:
======= cut here =========
set LIB_NAME "LCPU"
set DFF_CKQ 0.2;
set DFF_SETUP 0.0;
set TOPLEVEL "cpu"
set GATE_PATH "/srv/software/synopsys/B-2008.09-SP3/libraries/syn/"
set CLK "in_clock"
set RST "in_reset"
set CLK_PERIOD 0.1;
set CLK_UNCERTAINTY 0.1;
set search_path [concat $search_path $GATE_PATH]
set target_library lsi_10k.db
set symbol_library lsi_10k.sdb
set synthetic_library dw_foundation.sldb
set link_library "* $target_library $synthetic_library"
set INSTR_BITS 32
set PC_BITS 32
set REAL_INSTRSEL_BITS 8
set IMEM_CYCLES 0
set IMEM_CYCLES_BITS 1
set power_preserve_rtl_hier_names "true"
set modules {memory2 regfile fetch decode exec mem writeback cpu}
foreach module $modules {
analyze -format verilog $module.v
elaborate $module
}
current_design $TOPLEVEL
rtl2saif -output cpu-forward.saif -design $TOPLEVEL
create_clock $CLK -period $CLK_PERIOD
set_clock_uncertainty $CLK_UNCERTAINTY [all_clocks]
set_dont_touch_network [all_clocks]
remove_driving_cell $RST
set_drive 0 $RST
set_dont_touch_network $RST
set_output_delay $DFF_SETUP -clock $CLK [all_outputs]
set_load 1.5 [all_outputs]
set all_inputs_wo_rst_clk [remove_from_collection
[remove_from_collection [all_inputs] [get_port $CLK]] [get_port $RST]]
set_input_delay -clock $CLK $DFF_CKQ $all_inputs_wo_rst_clk
link
uniquify
check_design
compile
write -format verilog -hierarchy -output cpu_gate.v
=======================
Some of this script was copied from other places, so it might be
wrong. So the resulting cpu_gate.v file should be a gate level
netlist that I can simulate with VCS, right? I tried simulating it
using the same testbench we used for the behavioral simulation, but
VCS gate me a bunch of missing module errors while elaborating it. So
I figured it was because VCS couldn't find the primitives in the
lsi_10k library, tried running these commands in dc_shell:
read_lib lsi_10k.lib
write_lib -f vhdl lsi_10k
This left me with three vhdl files: lsi_10k_Vcomponents.vhd
lsi_10k_VITAL.vhd lsi_10k_Vtables.vhd
I tried including them in the simulation by running vhdlan on them
after running vlogan on the rest of the design and the testbench.
That didn't work either.
So, I know I might be completely barking up the wrong tree right now,
but I'm hoping someone here might be able to show me the right one.
Any ideas?
Oh, and I'm sure there's a book somewhere that explains how to do all
this stuff. Could someone point out a good one for me to get?
Thanks in advance,
Pete
I hope someone here can help me The group at my university
received licenses from Synopsys for their suite of tools, and a few of
us students have been given the task of trying to figure out how to
use them. Unfortunately, no one here has any prior experience with
them, and the documentation that comes with it is quite terse and
doesn't explain some of the finer details.
In any case, we've designed a very simple CPU model in verilog, and
we've been successful in doing a behavioral simulation with VCS. So I
figured I'd try doing a gate-level simulation next, because after that
I want to do power usage analysis on the design.
So in any case, we wrote this script to do the synthesis:
======= cut here =========
set LIB_NAME "LCPU"
set DFF_CKQ 0.2;
set DFF_SETUP 0.0;
set TOPLEVEL "cpu"
set GATE_PATH "/srv/software/synopsys/B-2008.09-SP3/libraries/syn/"
set CLK "in_clock"
set RST "in_reset"
set CLK_PERIOD 0.1;
set CLK_UNCERTAINTY 0.1;
set search_path [concat $search_path $GATE_PATH]
set target_library lsi_10k.db
set symbol_library lsi_10k.sdb
set synthetic_library dw_foundation.sldb
set link_library "* $target_library $synthetic_library"
set INSTR_BITS 32
set PC_BITS 32
set REAL_INSTRSEL_BITS 8
set IMEM_CYCLES 0
set IMEM_CYCLES_BITS 1
set power_preserve_rtl_hier_names "true"
set modules {memory2 regfile fetch decode exec mem writeback cpu}
foreach module $modules {
analyze -format verilog $module.v
elaborate $module
}
current_design $TOPLEVEL
rtl2saif -output cpu-forward.saif -design $TOPLEVEL
create_clock $CLK -period $CLK_PERIOD
set_clock_uncertainty $CLK_UNCERTAINTY [all_clocks]
set_dont_touch_network [all_clocks]
remove_driving_cell $RST
set_drive 0 $RST
set_dont_touch_network $RST
set_output_delay $DFF_SETUP -clock $CLK [all_outputs]
set_load 1.5 [all_outputs]
set all_inputs_wo_rst_clk [remove_from_collection
[remove_from_collection [all_inputs] [get_port $CLK]] [get_port $RST]]
set_input_delay -clock $CLK $DFF_CKQ $all_inputs_wo_rst_clk
link
uniquify
check_design
compile
write -format verilog -hierarchy -output cpu_gate.v
=======================
Some of this script was copied from other places, so it might be
wrong. So the resulting cpu_gate.v file should be a gate level
netlist that I can simulate with VCS, right? I tried simulating it
using the same testbench we used for the behavioral simulation, but
VCS gate me a bunch of missing module errors while elaborating it. So
I figured it was because VCS couldn't find the primitives in the
lsi_10k library, tried running these commands in dc_shell:
read_lib lsi_10k.lib
write_lib -f vhdl lsi_10k
This left me with three vhdl files: lsi_10k_Vcomponents.vhd
lsi_10k_VITAL.vhd lsi_10k_Vtables.vhd
I tried including them in the simulation by running vhdlan on them
after running vlogan on the rest of the design and the testbench.
That didn't work either.
So, I know I might be completely barking up the wrong tree right now,
but I'm hoping someone here might be able to show me the right one.
Any ideas?
Oh, and I'm sure there's a book somewhere that explains how to do all
this stuff. Could someone point out a good one for me to get?
Thanks in advance,
Pete