V
Verictor
Guest
Hi,
I am running a gate-level simulation. The message is this:
ncelab: *F, CUMSTS: Timescale directive missing on one or more modules
I then ensured the message is for the library *.v file. I don't know
if I need to specify the timescale in the library file. I really doubt
if I need to do that since I am not suppose to touch it. Anyway, there
seem other problems. When I tried to run the simulation no matter
what, it gave me another error:
Simulator "Design::" terminated abnormally. Use File->Open Simulation
to open a connection to another simulator.
What does that mean? RTL simulation works fine in this case.
Thanks.
I am running a gate-level simulation. The message is this:
ncelab: *F, CUMSTS: Timescale directive missing on one or more modules
I then ensured the message is for the library *.v file. I don't know
if I need to specify the timescale in the library file. I really doubt
if I need to do that since I am not suppose to touch it. Anyway, there
seem other problems. When I tried to run the simulation no matter
what, it gave me another error:
Simulator "Design::" terminated abnormally. Use File->Open Simulation
to open a connection to another simulator.
What does that mean? RTL simulation works fine in this case.
Thanks.