K
Kelvin
Guest
My design timing was 13.2ns...Now I am asked to do regressive compilation
with clock from 24:step(-2):8ns...odd experiment...Basically I put a
"foreach" then
"reset_design" and "compile -map_effort medium" for each timing
constraint...
Now I am done with 24ns and 22 ns...at 24ns, the area was 700114.062500,
while at 22ns it's 698171.437500...the gate count is 69KG+- though...
How do I explain this behavior to the other engineers ;-)
Kelvin
with clock from 24:step(-2):8ns...odd experiment...Basically I put a
"foreach" then
"reset_design" and "compile -map_effort medium" for each timing
constraint...
Now I am done with 24ns and 22 ns...at 24ns, the area was 700114.062500,
while at 22ns it's 698171.437500...the gate count is 69KG+- though...
How do I explain this behavior to the other engineers ;-)
Kelvin