P
Praveen
Guest
Hi all,
I have been looking at some code that raised a basic question. If we
have process like
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
when trigger is true are the 4 signal assignment statements executed
sequentially or concurrently ?
What happens when they are variable assignments like below
process
begin
wait on TRIGGER;
variable1 := Variable2;
Variable2 := Variable1 + Variable3;
Variable3 := signal2;
RESULT <= Variable1 + Variable2 + Variable3; -- RESULT is of
type signal
end process;
I tried simulating both of them and the results are different (because
of the variable/signal differnce on assignment).
The website where this example is cited
http://www.seas.upenn.edu/~ee201/vhdl/vhdl_primer.html#_Toc526061350
says ..when they are declared as variables they are executed
sequentially and when declared as signals are executed concurrently.
The book that I usually follow says (and I agree) that the signal
assignments are sequentially executed. Is'nt that the reason why
processes were created in the first place?
If they are executed sequentially, why do we get the different values
when they are declared as variables/signals.
Could someone help me out?
Thanks.
I have been looking at some code that raised a basic question. If we
have process like
process
begin
wait on TRIGGER;
signal1 <= signal2;
signal2 <= signal1 + signal3;
signal3 <= signal2;
RESULT <= signal1 + signal2 + signal3;
end process;
when trigger is true are the 4 signal assignment statements executed
sequentially or concurrently ?
What happens when they are variable assignments like below
process
begin
wait on TRIGGER;
variable1 := Variable2;
Variable2 := Variable1 + Variable3;
Variable3 := signal2;
RESULT <= Variable1 + Variable2 + Variable3; -- RESULT is of
type signal
end process;
I tried simulating both of them and the results are different (because
of the variable/signal differnce on assignment).
The website where this example is cited
http://www.seas.upenn.edu/~ee201/vhdl/vhdl_primer.html#_Toc526061350
says ..when they are declared as variables they are executed
sequentially and when declared as signals are executed concurrently.
The book that I usually follow says (and I agree) that the signal
assignments are sequentially executed. Is'nt that the reason why
processes were created in the first place?
If they are executed sequentially, why do we get the different values
when they are declared as variables/signals.
Could someone help me out?
Thanks.