Functions with unconstrained array inputs (Verilog 2001/Sys

[Amal]

This question has come up a few time I suppose, but I still cannot
believe that functions with unconstrained arrays as their input or
output is not supported (specifically for synthesis). There are many
different situations that I would like to write some generic code that
is reused among many blocks. I understand that one might be able to
write it as a parameterized module instead of a function call. But I
still believe a generic function call would be a much more natural
view of a problem.

Especially with the addition of SystemVerilog packages and classes I
thought this would be a breeze. And my other disappointment was that
classes are not synthesizable. Again, I could think of many
situations that a syntheziable class (whether a subset of its features
or not), would be a great addition.

Does anyone have any suggestion for writing synthesizable, reusable
code similar to functions with unconstrained arrays in VHDL? NOT
using modules, tasks, or include files.

-- Amal

 

[Mike Treseler]

Amal wrote:

Does anyone have any suggestion for writing synthesizable, reusable
code similar to functions with unconstrained arrays in VHDL? NOT
using modules, tasks, or include files.

I might consider *using* vhdl for those modules,
and using the system verilog packages and classes
for verification.
FPGA synthesis covers both verilog and vhdl modules.


-- Mike Treseler

 

On Apr 7, 9:21 am, Amal <akhailt...@gmail.com> wrote:

This question has come up a few time I suppose, but I still cannot
believe that functions with unconstrained arrays as their input or
output is not supported (specifically for synthesis).

In SystemVerilog, dynamic arrays could be used in some such
situations. However, they would not handle everything that you would
want. They allow a function to accept or return an arbitrarily sized
array, but that array must be a dynamic array at the caller as well.
They cannot be used to write a function that accepts and returns an
arbitrary sized fixed-size array.

For that reason, I would not expect synthesis tools to support them.
In theory, such tools could do analysis to determine that the dynamic
arrays are initialized to a constant size that is never modified, and
that the function does not modify its size. In that case, it might be
possible to treat them much like VHDL unconstrained arrays. However,
I would not expect tools to support that, at least not yet.

Also, dynamic arrays are unpacked arrays. There are no operators that
treat the array as a whole as a numeric or bit-vector value. That is
only possible with packed arrays, which represent bit-vectors or
numbers, and those are always fixed size. You could use "operator
overloading" to define operators that acted on dynamic arrays, but I
would not expect tools to be supporting that yet either. I would also
expect that simulation of such operations would become about as slow
as VHDL simulation of such operations, instead of the much faster
implementation possible with native Verilog vector types. There are
some advantages of the Verilog representation over VHDL.

 

[Kevin Neilson]

Amal wrote:

This question has come up a few time I suppose, but I still cannot
believe that functions with unconstrained arrays as their input or
output is not supported (specifically for synthesis). There are many
different situations that I would like to write some generic code that
is reused among many blocks. I understand that one might be able to
write it as a parameterized module instead of a function call. But I
still believe a generic function call would be a much more natural
view of a problem.

Especially with the addition of SystemVerilog packages and classes I
thought this would be a breeze. And my other disappointment was that
classes are not synthesizable. Again, I could think of many
situations that a syntheziable class (whether a subset of its features
or not), would be a great addition.

Does anyone have any suggestion for writing synthesizable, reusable
code similar to functions with unconstrained arrays in VHDL? NOT
using modules, tasks, or include files.

-- Amal
I like the VHDL concept of having port sizes be unconstrained and wish

that synthesizers (like Synplify) would adopt the SystemVerilog support
of this, so one could use the SystemVerilog size() function with Verilog
to determine a port width instead of having to pass the size through a
parameter.

I have written synthesizable functions in Verilog which model
unconstrained behavior, using a parameter. But it's still better than a
module. I wrote an LFSR (which I can't find now) which used a function
call something like this:

parameter LFSR_SIZE = 12;
reg [LFSR_SIZE-1:0] lfsr_reg = 0;
always@(posedge clk) lfsr_reg <= lfsr(lfsr_reg,LFSR_SIZE);

The function lfsr() always returned 32 bits, but only the
least-significant LFSR_SIZE bits are assigned to lfsr_reg. LFSR_SIZE
also determined the feedback taps used. This function was synthesizable
and pseudo-unconstrained. It's nicely abstract, though as a function
call it can't be explicitly pipelined.
-Kevin