Functional VHDL Simulation Problem with Altera dual clock fi

[Thomas Fischer]

Altera Modelsim 5.8e

I'm new to modelsim and try to make a functional simulation for a
project with an
Altera Fifo (dcfifo).

I get the following simulation error:
last value in fifo cannot be read, rdempty flag toggles when last
value is tried to read.

the problem only occures, if a signal is used as the rdclk,
if the rdclk is taken directly from the entity port clk_i everything
works fine.

...
...
begin

txf_rdclk <= clk_i; -- problem if txf_rdclk is used in port map

txfifo : dcfifo0
PORT MAP (
wrclk => wrclk_i,
rdreq => txf_rdreq,
aclr => rst_i,
rdclk => txf_rdclk, -- problem if txf_rdclk is used in port map
-- rdclk => clk_i, -- this works fine
wrreq => wrreq_i,
data => data_i,
rdfull => txf_rdfull,
rdempty => txf_rdempty,
wrusedw => txf_wrusedw,
wrfull => txf_wrfull_o,
wrempty => txf_wrempty,
q => txf_q,
rdusedw => txf_rdusedw
);
...
...

why does i have problems with the signal txf_rdclk ?