V
Vazquez
Guest
Dear Sir or Madame,
I have a question concerning the inputs of a VHDL module when
simulating with the Altera QuartusII Waveform Editor.
The input CONTROL shall be a registered signal from a different
module.
When doing a functional simulation I edit the waveform in that form you
can see so that CONTROL changes its value right with rising edge of
CLK. So I want to reproduce the registered input signal CONTROL.
But when starting the functional simulation I get the error message:
"Found clock-sensitive change during active clock edge ...", of course.
My question: How can I reproduce the clock synchronous input CONTROL without
violating setup-time? (using the Waveform Editor !!!)
Thank you for your help.
Andre V.
G&D System Development
-------- -------- --------
| | | | | |
| | | | | | CLK
| |___________| |___________| |___________
-------------------------------------------
|
| CONTROL
_____________________|
I have a question concerning the inputs of a VHDL module when
simulating with the Altera QuartusII Waveform Editor.
The input CONTROL shall be a registered signal from a different
module.
When doing a functional simulation I edit the waveform in that form you
can see so that CONTROL changes its value right with rising edge of
CLK. So I want to reproduce the registered input signal CONTROL.
But when starting the functional simulation I get the error message:
"Found clock-sensitive change during active clock edge ...", of course.
My question: How can I reproduce the clock synchronous input CONTROL without
violating setup-time? (using the Waveform Editor !!!)
Thank you for your help.
Andre V.
G&D System Development
-------- -------- --------
| | | | | |
| | | | | | CLK
| |___________| |___________| |___________
-------------------------------------------
|
| CONTROL
_____________________|