function with 2d return type

[Maki - (Remove 123 to mai]

Hello all,

I'm trying to code a function that initialize some vars from a file.
Function should reside in separate package and my intention is to use it for
different size and width of return type without manual correction whenever
design changes.
Something like:
load_hex_from_file(file_name:string; depth,bits:natural) return
2d_array_type;

2d_array_type should be parametrizable and should inherit type from variable
that receives data.
Do You have an idea how to accomplish this without special (custom) type
conversion functions?
At the moment variable in a separate package that needs init is defined like
this:
type ram_memory is array (0 to (2**(depth+1))-1) of std_logic_vector(bits-1
downto 0);
Any ideas?

Best regards,
M.

--
M. Veselic
Sigma Lab.

 

[Rob Dekker]

"Maki - (Remove 123 to mail me)" <123veselic@eunet.yu> wrote in message news:dps1de$b2e$1@news.eunet.yu...

Hello all,

I'm trying to code a function that initialize some vars from a file.
Function should reside in separate package and my intention is to use it for
different size and width of return type without manual correction whenever
design changes.
Something like:
load_hex_from_file(file_name:string; depth,bits:natural) return
2d_array_type;

2d_array_type should be parametrizable and should inherit type from variable
that receives data.
Do You have an idea how to accomplish this without special (custom) type
conversion functions?
At the moment variable in a separate package that needs init is defined like
this:
type ram_memory is array (0 to (2**(depth+1))-1) of std_logic_vector(bits-1
downto 0);
Any ideas?

Maki,

I assume that you want to use your 'load_hex_from_file' function to initialize a signal
of type 'ram_memory' ?

Well, since VHDL is strongly typed, the return type of the function should be 'ram_memory'.
With that, the index ranges of the returned value are defined and consistent with the
target signal that you want to initialize. Remember that if 'load_hex_from_file' returns
a value that does NOT have the exact number of elements needed for the target signal,
that your simulator will give an error any way. So let the function return 'ram_memory' type.

Does this help ?

Rob

Best regards,
M.

--
M. Veselic
Sigma Lab.

 

[Maki - (Remove 123 to mai]

"Rob Dekker" <rob@verific.com> wrote in message
news:OtZwf.26407$UF3.3102@newssvr25.news.prodigy.net...

"Maki - (Remove 123 to mail me)" <123veselic@eunet.yu> wrote in message
news:dps1de$b2e$1@news.eunet.yu...
Hello all,

I'm trying to code a function that initialize some vars from a file.
Function should reside in separate package and my intention is to use it
for
different size and width of return type without manual correction
whenever
design changes.
Something like:
load_hex_from_file(file_name:string; depth,bits:natural) return
2d_array_type;

2d_array_type should be parametrizable and should inherit type from
variable
that receives data.
Do You have an idea how to accomplish this without special (custom) type
conversion functions?
At the moment variable in a separate package that needs init is defined
like
this:
type ram_memory is array (0 to (2**(depth+1))-1) of
std_logic_vector(bits-1
downto 0);
Any ideas?

Maki,

I assume that you want to use your 'load_hex_from_file' function to
initialize a signal
of type 'ram_memory' ?

Well, since VHDL is strongly typed, the return type of the function should
be 'ram_memory'.
With that, the index ranges of the returned value are defined and
consistent with the
target signal that you want to initialize. Remember that if
'load_hex_from_file' returns
a value that does NOT have the exact number of elements needed for the
target signal,
that your simulator will give an error any way. So let the function return
'ram_memory' type.

Does this help ?

Rob

Hi Rob,
Thanks for Your answer
The problem is I don't want to peek into details of ram_memory type. It is
in a separate package on which I dont want to depend. Unfortunatly there is
no base standard type that is 2dim, so if I make my own type i have to
provide a package for conversion of that type to any other that I'm going to
use such as ram_memory or whatever.
I have tried an unconstrained array of (for example) std_logic_vector, but
the simulator is unhappy probably because standard does not allow such a
nonsense ). It would bi nice if I could to this :
load_hex_from_file(file_name:string; depth,bits:natural) return is array (0
to depth-1) of std_logic_vector(bits-1 downto 0) ;
Maybe I'm going to far with this. After all it is not such a big problem to
change those types to match.
Thanks anyway
Cheers,

--
M. Veselic
Sigma Lab.