Function returns binary result

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valtih1978

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I see a scersity of examples of function declaration but only integers,
reals and bit_vectors. Nobody demonstrates how do declare the simple
binary result. I conclude that there is no way to specify a binary
result type
 
valtih1978 wrote:
I see a scersity of examples of function declaration but only integers,
reals and bit_vectors. Nobody demonstrates how do declare the simple
binary result. I conclude that there is no way to specify a binary
result type
It's not clear what you're looking for. A function can have a range
like:

function [7:0] foo;

So if you mean you want to return 1 bit it could probably look like:

function [0:0] foo;

But in Verilog, you can always assign an integer to a single-bit
variable as long as you understand that you're getting the LSB
of the integer. There's no separate "Boolean" type like you might
have in VHDL.

-- Gabor
 
Excuse, me. I start to repeat those mistakes and beg for more
int/bitvectors examples under the pretext that they overflood the simple
bit/boolean type declaration. I have discovered that it is "reg", which
declares a single bit:

function reg diff; // value of reg type is produced
input [width-1:0] ref;
input [width-1:0] val;

integer i;
begin
diff = 0;
for ( i = 0 ; i != width ; i = i+1)

// X-masking
if (ref !== 1'bX & val !== ref)
diff = 1;

end
endfunction

which is not obvious at all.
 
valtih1978 wrote:
Excuse, me. I start to repeat those mistakes and beg for more
int/bitvectors examples under the pretext that they overflood the simple
bit/boolean type declaration. I have discovered that it is "reg", which
declares a single bit:

function reg diff; // value of reg type is produced
input [width-1:0] ref;
input [width-1:0] val;

integer i;
begin
diff = 0;
for ( i = 0 ; i != width ; i = i+1)

// X-masking
if (ref !== 1'bX & val !== ref)
diff = 1;

end
endfunction

which is not obvious at all.

I was working from the Doulos "Golden reference guide" which does not
show "reg" as an appropriate type for functions. Their syntax is
shown as:

function [automatic] [signed] [<Range_or_type>] FunctionName
[(<FunctionPorts,...)];

where <Range_or_Type> can be a range like [7:0]
or one of: integer, time, real, or realtime

Note that reg is not one of the types listed, however it may have been
overlooked, or you may be using tools that support newer constructs
since Verilog 2001.

On the other hand, my point was that you don't really _need_
to have a function return a single bit most of the time. The
only time I can think would be if you were going to concatenate
the return values without first assigning them to a wire or
reg. As you can see in your own example, if you have a 1-bit
reg ("diff" in your case) you can still assign it an integer
value of 0 or 1, and get the same results as if you had
assigned 1'b0 or 1'b1. So you could use the function like:

reg foo;

always @ (something or other)
foo <= diff (a,b);

And it would make no difference in this context whether the function
"diff" was defined as a single bit or an integer, since in either
case foo will get the LSB of the return value.

-- Gabor
 
On 1/23/2013 6:17 AM, GaborSzakacs wrote:
valtih1978 wrote:

function reg diff; // value of reg type is produced
input [width-1:0] ref;
input [width-1:0] val;
integer i;
begin
diff = 0;
for ( i = 0 ; i != width ; i = i+1)
// X-masking
if (ref !== 1'bX & val !== ref)
diff = 1;
end
endfunction


Note that reg is not one of the types listed, however it may have been
overlooked, or you may be using tools that support newer constructs
since Verilog 2001.

I believe reg only works for SystemVerilog. Using [0:0] is more
portable, but that implies a one bit vector which is subtly different
from a scalar. The portable way to return a scalar is to omit the type
completely (e.g. function diff;)

From 1364-2001 "The use of a range_or_type shall be optional. A
function specified without a range or type defaults to a one bit reg for
the return value."

I will also recommend changing the code to use the logic AND '&&'
instead of the bit-wise AND '&'. In some situation using the wrong one
can create subtle bugs (e.g. 2'b10 & 2'b01 equates to 2'b00 which is not
true while 2'b10 && 2'b01 returns 1'b1 which is true).

Cary
 

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