L
leon
Guest
Is there a reason why function overloading was not thought of during
the development of verilog 2k and system verilog. This is something
VHDL handles well - why didnt the Verilog committee want to support it.
Currently the only way to support this is to declare a module for a
function and use a parameter to over-ride. Not the best way to write
code. Any comments anyone??
the development of verilog 2k and system verilog. This is something
VHDL handles well - why didnt the Verilog committee want to support it.
Currently the only way to support this is to declare a module for a
function and use a parameter to over-ride. Not the best way to write
code. Any comments anyone??