function call with empty argument list, parenthesis and assi

[valtih1978]

My parser accepts this

$random(1); // ok
$random(); // ok

but fails when assignment is involved

a = $random(); // parser syntax error

Modelsim accepts everything. I have checked the LRM,
http://www.verilog.com/VerilogBNF.html#REF161, which says

<function_call>
::= <name_of_function> ( <expression> <,<expression>>* )
||= <name_of_system_function> ( <expression> <,<expression>>* )
||= <name_of_system_function>

It seems that parenthesis demand an argument. What is correct?

 

[Cary R.]

On 6/3/2013 8:36 AM, valtih1978 wrote:

My parser accepts this

$random(1); // ok
$random(); // ok

but fails when assignment is involved

a = $random(); // parser syntax error

Modelsim accepts everything. I have checked the LRM,
http://www.verilog.com/VerilogBNF.html#REF161, which says

function_call
::= <name_of_function> ( <expression> <,<expression>>* )
||= <name_of_system_function> ( <expression> <,<expression>>* )
||= <name_of_system_function

It seems that parenthesis demand an argument. What is correct?

The simple answer is it depends on if you are parsing Verilog or
SystemVerilog. From what you have shown it looks like you are parsing
this as Verilog while Modelsim is parsing it as SystemVerilog. Here is
my analysis.

Your first two examples are likely passing because your parser thinks
those statements are calls to a task names $random not a function names
$random. Previous versions of Verilog required a function to have at
least one argument inside parenthesis or a system function would omit
the empty parenthesis pair if it had no arguments (e.g. a = $random.
This is what the BNF you showed represents. SystemVerilog changes all
this by allowing a function to be called as a task and also a function
can be called with an empty parenthesis pair.

If you want to deal with SystemVerilog the latest version of the
standard (1800-2012) can be downloaded for free from the IEEE.

Cary