Fully defined case statement?

[Allen Sun]

Question about case statement, for example:

case (sel)
1'b0: dataout = a;
1'b1: dataout = b;
endcase

Is this fully defined case statement?
How about sel = 'x' or 'z'? Because I know case statement can
distinguish '0', '1', 'x', 'z'.

Thanks.

 

[John_H]

The casex or casez construct will distinguish the unknown inputs, requiring
additional entries for the unknowns. Note that the casex and casez won't
give you synthesizeable code for the x and z inputs - simulation only. For
simulation, any undefined states should result in an "x" for your output to
make proper sense.

A case should provide unknown outputs for unknown inputs and will not
distinguish the "x" and "z" the way you expect.


"Allen Sun" <xfsun@hotmail.com> wrote in message
news:47772f75.0306250901.2ffdaa64@posting.google.com...

Question about case statement, for example:

case (sel)
1'b0: dataout = a;
1'b1: dataout = b;
endcase

Is this fully defined case statement?
How about sel = 'x' or 'z'? Because I know case statement can
distinguish '0', '1', 'x', 'z'.

Thanks.

 

[Rajkumar]

xfsun@hotmail.com (Allen Sun) wrote in message news:<47772f75.0306250901.2ffdaa64@posting.google.com>...

Question about case statement, for example:

case (sel)
1'b0: dataout = a;
1'b1: dataout = b;
endcase

Is this fully defined case statement?
How about sel = 'x' or 'z'? Because I know case statement can
distinguish '0', '1', 'x', 'z'.

Thanks.

Hi!
The above statement is fully defined.
In real hardware there are only "0" & "1".
And yes there are case statements like casex & casez supported in
verilog.
They are used in hardware description if you want to ignore the input.
For e.g. in address decoder
casez(sel)
4'b1??? :
4'b01?? :
4'b00?? :
endcase

 

[Allen Sun]

rkadam@hotvoice.com (Rajkumar) wrote in message news:<6851e510.0306251651.39bf81c2@posting.google.com>...

xfsun@hotmail.com (Allen Sun) wrote in message news:<47772f75.0306250901.2ffdaa64@posting.google.com>...
Question about case statement, for example:

case (sel)
1'b0: dataout = a;
1'b1: dataout = b;
endcase

Is this fully defined case statement?
How about sel = 'x' or 'z'? Because I know case statement can
distinguish '0', '1', 'x', 'z'.

Thanks.

Hi!
The above statement is fully defined.
In real hardware there are only "0" & "1".
And yes there are case statements like casex & casez supported in
verilog.
They are used in hardware description if you want to ignore the input.
For e.g. in address decoder
casez(sel)
4'b1??? :
4'b01?? :
4'b00?? :
endcase

Hi,
Got it, thanks!

Allen