Fully definable ports of array of std_logic_vectors?

Guest
Hello,

I have a construct that I would like to build to have fully definable
ports which are arrays of std_logic_vectors, but from what I have
read, I haven't figured out yet a way to do this in
VHDL-1987/1993/2002. It seems that this will be possible in
VHDL-200X. Does anybody know a way that I could create a functional
equivalent to this using one of today's standards? I don't think that
using a package to define the types is really an option since I will
be instantiating multiple copies of this in the same design with
different array and vector lengths (correct me if I'm wrong).

Thanks for the help!
John

entity sample is

generic (
array_length_g : positive := 4;
vector_length_g : positive := 12);
port (
clk : in std_logic;
clk_enable : in std_logic;
reset_n : in std_logic;
input : in array(0 to array_length_g-1) of
std_logic_vector(vector_length_g-1 downto 0);
output : out array(0 to array_length_g-1) of
std_logic_vector(vector_length_g-1 downto 0);

end sample;
 
On Dec 12, 12:57 pm, paragon.j...@gmail.com wrote:
Hello,

I have a construct that I would like to build to have fully definable
ports which are arrays of std_logic_vectors, but from what I have
read, I haven't figured out yet a way to do this in
VHDL-1987/1993/2002. It seems that this will be possible in
VHDL-200X. Does anybody know a way that I could create a functional
equivalent to this using one of today's standards? I don't think that
using a package to define the types is really an option since I will
be instantiating multiple copies of this in the same design with
different array and vector lengths (correct me if I'm wrong).
Click to expand...
You have to use a two dimensional array. First define a new type that
is a two dimensional array of std_ulogic (or std_logic if you'd
prefer).

type sulv2d is array(natural range<>, natural range<>) of std_ulogic;

Now you use that type on your entity
input : in sulv2d(0 to array_length_g-1,vector_length_g-1 downto
0);

It works and is synthesizable.

KJ
 
On Dec 12, 2:32 pm, KJ <Kevin.Jenni...@unisys.com> wrote:
On Dec 12, 12:57 pm, paragon.j...@gmail.com wrote:

Hello,

I have a construct that I would like to build to have fully definable
ports which are arrays of std_logic_vectors, but from what I have
read, I haven't figured out yet a way to do this in
VHDL-1987/1993/2002. It seems that this will be possible in
VHDL-200X. Does anybody know a way that I could create a functional
equivalent to this using one of today's standards? I don't think that
using a package to define the types is really an option since I will
be instantiating multiple copies of this in the same design with
different array and vector lengths (correct me if I'm wrong).

You have to use a two dimensional array. First define a new type that
is a two dimensional array of std_ulogic (or std_logic if you'd
prefer).

type sulv2d is array(natural range<>, natural range<>) of std_ulogic;

Now you use that type on your entity
input : in sulv2d(0 to array_length_g-1,vector_length_g-1 downto
0);

It works and is synthesizable.

KJ
Click to expand...
I think what the OP is concerned about is that the length of the
elements in the array must also be defined in the package (per 2002
and earlier std), which then limits instances to always using that
same element length.

For a completely flexible interface, I would simply use an
SLV(array_length_g*vector_length_g - 1 downto 0) for the port, and
then in the architecture declare the array of vectors from the
generics, and declare functions to convert back and forth between the
flat vector and the array of vectors.

Not as clean as he wants, but until 200x is implemented, I don't know
of other choices that meet his needs.

Andy
 
"Andy" <jonesandy@comcast.net> wrote in message
news:b53be4d6-3899-4606-a9cb-89bc5a39387f@e10g2000prf.googlegroups.com...
On Dec 12, 2:32 pm, KJ <Kevin.Jenni...@unisys.com> wrote:
On Dec 12, 12:57 pm, paragon.j...@gmail.com wrote:


You have to use a two dimensional array. First define a new type that
is a two dimensional array of std_ulogic (or std_logic if you'd
prefer).

type sulv2d is array(natural range<>, natural range<>) of std_ulogic;

Now you use that type on your entity
input : in sulv2d(0 to array_length_g-1,vector_length_g-1 downto
0);

It works and is synthesizable.

KJ

I think what the OP is concerned about is that the length of the
elements in the array must also be defined in the package (per 2002
and earlier std), which then limits instances to always using that
same element length.

Yes, and both the two dimensional array solution that I proposed and the one
Click to expand...
dimensional one that you propose both accomplish that.

For a completely flexible interface, I would simply use an
SLV(array_length_g*vector_length_g - 1 downto 0) for the port, and
then in the architecture declare the array of vectors from the
generics, and declare functions to convert back and forth between the
flat vector and the array of vectors.

The one-d approach has an advantage if the synthesis tool does not support
Click to expand...
two-d. Other than that they are essentially equivalent. Both will require
copy/paste conversion functions so that one can work with things like
address(2) and mean the entire address bus.

The two-d approach has a readability advantage, you don't have to multiply
in your head to figure out that address(213) is bit 13 of the 21st entry
(zero based) of an array of 10 bit addresses. Using two-d that same bit
would be address(21)(13).

KJ
 
On Dec 17, 10:33 am, "KJ" <kkjenni...@sbcglobal.net> wrote:
"Andy" <jonesa...@comcast.net> wrote in message

news:b53be4d6-3899-4606-a9cb-89bc5a39387f@e10g2000prf.googlegroups.com...

On Dec 12, 2:32 pm, KJ <Kevin.Jenni...@unisys.com> wrote:
On Dec 12, 12:57 pm, paragon.j...@gmail.com wrote:

You have to use a two dimensional array. First define a new type that
is a two dimensional array of std_ulogic (or std_logic if you'd
prefer).

type sulv2d is array(natural range<>, natural range<>) of std_ulogic;

Now you use that type on your entity
input : in sulv2d(0 to array_length_g-1,vector_length_g-1 downto
0);

It works and is synthesizable.

KJ

I think what the OP is concerned about is that the length of the
elements in the array must also be defined in the package (per 2002
and earlier std), which then limits instances to always using that
same element length.

Yes, and both the two dimensional array solution that I proposed and the one
dimensional one that you propose both accomplish that.

For a completely flexible interface, I would simply use an
SLV(array_length_g*vector_length_g - 1 downto 0) for the port, and
then in the architecture declare the array of vectors from the
generics, and declare functions to convert back and forth between the
flat vector and the array of vectors.

The one-d approach has an advantage if the synthesis tool does not support
two-d. Other than that they are essentially equivalent. Both will require
copy/paste conversion functions so that one can work with things like
address(2) and mean the entire address bus.

The two-d approach has a readability advantage, you don't have to multiply
in your head to figure out that address(213) is bit 13 of the 21st entry
(zero based) of an array of 10 bit addresses. Using two-d that same bit
would be address(21)(13).

KJ
Click to expand...
Thanks, I did not realize that multi-dimensioned array typedefs
allowed all index ranges to be unconstrained (as opposed to arrays of
arrays, where the inner array index must be constrained in the outer
array typedef for vhdl 2002 and earlier).

Learn something new every day....

Andy
 
On Dec 17, 2:16 pm, Andy <jonesa...@comcast.net> wrote:
On Dec 17, 10:33 am, "KJ" <kkjenni...@sbcglobal.net> wrote:



"Andy" <jonesa...@comcast.net> wrote in message

news:b53be4d6-3899-4606-a9cb-89bc5a39387f@e10g2000prf.googlegroups.com...

On Dec 12, 2:32 pm, KJ <Kevin.Jenni...@unisys.com> wrote:
On Dec 12, 12:57 pm, paragon.j...@gmail.com wrote:

You have to use a two dimensional array. First define a new type that
is a two dimensional array of std_ulogic (or std_logic if you'd
prefer).

type sulv2d is array(natural range<>, natural range<>) of std_ulogic;

Now you use that type on your entity
input : in sulv2d(0 to array_length_g-1,vector_length_g-1 downto
0);

It works and is synthesizable.

KJ

I think what the OP is concerned about is that the length of the
elements in the array must also be defined in the package (per 2002
and earlier std), which then limits instances to always using that
same element length.

Yes, and both the two dimensional array solution that I proposed and the one
dimensional one that you propose both accomplish that.

For a completely flexible interface, I would simply use an
SLV(array_length_g*vector_length_g - 1 downto 0) for the port, and
then in the architecture declare the array of vectors from the
generics, and declare functions to convert back and forth between the
flat vector and the array of vectors.

The one-d approach has an advantage if the synthesis tool does not support
two-d. Other than that they are essentially equivalent. Both will require
copy/paste conversion functions so that one can work with things like
address(2) and mean the entire address bus.

The two-d approach has a readability advantage, you don't have to multiply
in your head to figure out that address(213) is bit 13 of the 21st entry
(zero based) of an array of 10 bit addresses. Using two-d that same bit
would be address(21)(13).

KJ

Thanks, I did not realize that multi-dimensioned array typedefs
allowed all index ranges to be unconstrained (as opposed to arrays of
arrays, where the inner array index must be constrained in the outer
array typedef for vhdl 2002 and earlier).

Learn something new every day....

Andy
Click to expand...
You can use multiD package that was posted here a while ago.

http://groups.google.com/group/comp.lang.vhdl/browse_thread/thread/bd9ea0e7f68c0122/5ede62767a3a0487?lnk=gst&q=multid+array+package#5ede62767a3a0487

Based on this idea I have been writing a new package that is very
similar to the Fortran array concept. The package is almost ready and
I will post it here as soon as I do some cleanup. You can get single
bits, a range (vector), or a section of an array by using scalar
index, a range using what I call tuple (lo, hi), or a range using what
I call a triplet (lo, hi, stride) or arbitrary indexes from the array
using a vector index.

Unfortunately this is done for std_logic(_vector) and by the time
VHDL-200x package generics come, you can have constraint array of
arrays too. So there will be no point in having this package by then.

For most applications this is overkill, but if you want to develop
fully generic components, you might need this. Lets say, for a
generic FIR filter with N taps, you need N coefficients each W bits
wide.

-- Amal
 
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