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gnuarm.del...@gmail.com
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I working on a design where there will be some five sigma-delta ADCs and several specific level detect inputs each using an LVDS input pair as a comparator. So I\'m pretty committed to this working.
The LVDS common mode range can work down to 50 mV and I\"ll be testing that. I need to sense the voltage across a FET in an H bridge for over current or open load.
The ADCs need to have decent resolution, 12 bits at a minimum. I\'ve seen an app note on this in a Lattice FPGA that achieved 12 bits. But it is hard to tell where the errors will creep in. It\'s not all about the noise. Non-linearity is also important.
I guess I\'ll have more info in a few weeks.
--
Rick C.
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The LVDS common mode range can work down to 50 mV and I\"ll be testing that. I need to sense the voltage across a FET in an H bridge for over current or open load.
The ADCs need to have decent resolution, 12 bits at a minimum. I\'ve seen an app note on this in a Lattice FPGA that achieved 12 bits. But it is hard to tell where the errors will creep in. It\'s not all about the noise. Non-linearity is also important.
I guess I\'ll have more info in a few weeks.
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209