full_case and parallel_case

[Jason Zheng]

This is a synplify-specific question:

Can you apply both directives to one case statement?

for example:

case (1) /* synthesis full_case, parallel_case */
state[0]: ...
state[1]: ...
endcase

 

[John_H]

I do it all the time but I don't use the comma. The help should point you
toward the multiple-parameter use for these directives.
/* synthesis full_case parallel_case */


"Jason Zheng" <jzheng@jpl.nasa.gov> wrote in message
news:co2oko$sa5$1@nntp1.jpl.nasa.gov...

This is a synplify-specific question:

Can you apply both directives to one case statement?

for example:

case (1) /* synthesis full_case, parallel_case */
state[0]: ...
state[1]: ...
endcase

 

[Jim Lewis]

Jason,
You probably also want to read Cliff's paper:
"full_case parallel_case", the Evil Twins of Verilog Synthesis

which is available at:
http://www.sunburst-design.com/papers/


Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

This is a synplify-specific question:

Can you apply both directives to one case statement?

for example:

case (1) /* synthesis full_case, parallel_case */
state[0]: ...
state[1]: ...
endcase

 

[Jason Zheng]

Jim Lewis wrote:

Jason,
You probably also want to read Cliff's paper:
"full_case parallel_case", the Evil Twins of Verilog Synthesis

which is available at:
http://www.sunburst-design.com/papers/


Cheers,
Jim
Thanks for pointing me to that paper. Great help.