FSM

[Shiv]

hello friends,

I have to do a project on FSM(Finite State Machine) pls suggest me how
should i start and what to do... as i never did any project in
verilog...

till now i have designed all the basic gates flip-flops, and decoder i
also have written verilog code for traffic signal control, from
Palnitkar...

please help me I have no time....

I will be highly thankfull to you


thanks in advance

shiv gopal

 

[Muzaffer Kal]

On Sat, 21 Jun 2008 00:12:39 -0700 (PDT), Shiv <shivgy@gmail.com>
wrote:

hello friends,

I have to do a project on FSM(Finite State Machine) pls suggest me how
should i start and what to do... as i never did any project in
verilog...

till now i have designed all the basic gates flip-flops, and decoder i
also have written verilog code for traffic signal control, from
Palnitkar...

The easiest solution to your problem is to open a new schematic in
your favorite schematic editor, draw your FSM schematic and then do a
verilog netlist generation assuming you know how to generate the gates
for the next state calculation of your FSM. The next step to entering
Verilog directly is to start with a bunch of DFFs:

DFF ustate0(.CLK(CLK), .RST(RST), .D(ds0), .Q(qs0));
DFF ustate1 ...

and the generate the wires:

and u0(ds0, qs0, qs1, qs2, ...);
or u1(ds1, qs0, qs4 ...);

You can just wrap this with a

module FSM(CLK, RST, IN, OUT);
input CLK, RST;
input [7:0] IN;
output [7:0] OUT;

buf ub0(OUT[0], qs0);

....

endmodule

Then finally you can start using behavioral constructs of the Verilog
to generate you ds0, ds1 etc signals and infer DFFs as opposed to
instantiating them and you have started designing digital circuits in
Verilog.

 

[Shiv]

On Jun 21, 12:55 pm, Muzaffer Kal <k...@dspia.com> wrote

The easiest solution to your problem is to open a new schematic in
your favorite schematic editor, draw your FSM schematic and then do a
verilog netlist generation assuming you know how to generate the gates
for the next state calculation of your FSM. The next step to entering
Verilog directly is to start with a bunch of DFFs:

DFF ustate0(.CLK(CLK), .RST(RST), .D(ds0), .Q(qs0));
DFF ustate1 ...

and the generate the wires:

and u0(ds0, qs0, qs1, qs2, ...);
or u1(ds1, qs0, qs4 ...);

You can just wrap this with a

module FSM(CLK, RST, IN, OUT);
input CLK, RST;
input [7:0] IN;
output [7:0] OUT;

buf ub0(OUT[0], qs0);

...

endmodule

Then finally you can start using behavioral constructs of the Verilog
to generate you ds0, ds1 etc signals and infer DFFs as opposed to
instantiating them and you have started designing digital circuits in
Verilog.

thanks for your suggestion but i still have problem, i am working on
red hat linux
and i am using test editor to write verilog codes for the desired
circuit and then its textbench...

wat you said i didn't understand please try to understand that i have
no any previous idea of verilog and i started working just two weaks
ago...

thanks again for your quick reply..

 

[Pinhas]

On 21 יוני, 11:54, Shiv <shi...@gmail.com> wrote:

On Jun 21, 12:55 pm, Muzaffer Kal <k...@dspia.com> wrote



The easiest solution to your problem is to open a new schematic in
your favorite schematic editor, draw your FSM schematic and then do a
verilog netlist generation assuming you know how to generate the gates
for the next state calculation of your FSM. The next step to entering
Verilog directly is to start with a bunch of DFFs:

DFF ustate0(.CLK(CLK), .RST(RST), .D(ds0), .Q(qs0));
DFF ustate1 ...

and the generate the wires:

and u0(ds0, qs0, qs1, qs2, ...);
or u1(ds1, qs0, qs4 ...);

You can just wrap this with a

module FSM(CLK, RST, IN, OUT);
input CLK, RST;
input [7:0] IN;
output [7:0] OUT;

buf ub0(OUT[0], qs0);

...

endmodule

Then finally you can start using behavioral constructs of the Verilog
to generate you ds0, ds1 etc signals and infer DFFs as opposed to
instantiating them and you have started designing digital circuits in
Verilog.

thanks for your suggestion but i still have problem, i am working on
red hat linux
and i am using test editor to write verilog codes for the desired
circuit and then its textbench...

wat you said i didn't understand please try to understand that i have
no any previous idea of verilog and i started working just two weaks
ago...

thanks again for your quick reply..

Some verilog/vhdl/regression scripts at http://bknpk.no-ip.biz/.
Some tricks for debug of FSM at http://bknpk.no-ip.biz/SDIO/enumerating.html..