FSM Problem

C

Charlie

Guest
Hello,

I'm trying to code a simple state machine in VHDL. When I simulate it it
seems to run okay, but when I run it for real inside an FPGA it just seems
to get stuck in the first state. The first state has an IF statement in it,
if I remove this IF statement the FSM runs without getting stuck. The
following shows how I have coded the FSM:

state_machine : process(RST, FAST_CLK)
begin
if RST = '0' then
fsm_state <= IDLE;
elsif FAST_CLK'event and FAST_CLK = '1' then
case fsm_state is
when IDLE =>
fsm_state <= STATE_00;

when STATE_00 =>
if SIG_A = SIG_B then -- just 2 signals
fsm_state <= STATE_01;
else
fsm_state <= STATE_02;
end if;

when STATE_01 =>
.
.
.

When I run the code in the FPGA it just gets stuck in STATE_00. FAST_CLK is
definatley running (I can see it on an oscilliscope) and the RST signal is
equal to 1. I know it's stuck in STATE_00 because I make the FPGA turn on
certain signals in certain states, I then watch the signals on a logic
analyzer. If I remove the IF statement and replace it with either
'fsm_state <= STATE_01' or 'fsm_state <= STATE_02' the fsm runs okay.

So, does anyone have any idea on what I'm doing wrong? I'm using the XILINX
ISE software. If anyone needs any further details then just let me know.

Thanks for any advice,
 
On Sat, 27 Dec 2003 23:03:11 -0800, "Charlie" <Charlie@no_spam.com>
wrote:

Hello,

I'm trying to code a simple state machine in VHDL. When I simulate it it
seems to run okay, but when I run it for real inside an FPGA it just seems
to get stuck in the first state. The first state has an IF statement in it,
if I remove this IF statement the FSM runs without getting stuck. The
following shows how I have coded the FSM:

state_machine : process(RST, FAST_CLK)
[...]

when STATE_00 =
if SIG_A = SIG_B then -- just 2 signals
fsm_state <= STATE_01;
else
fsm_state <= STATE_02;
end if;


So, does anyone have any idea on what I'm doing wrong? I'm using the XILINX
ISE software. If anyone needs any further details then just let me know.
Click to expand...

Not sure. First problem is the meaning of "=" between two signals, where
those signals may be "X" or "U" for example (assuming they are of type
std_logic, and driven correctly)

To_01(Sig_A) forces the unknown values into known (0,1) states, which
could help if the problem were seen in simulation.

Alternatively
when STATE_00 =
fsm_state <= STATE_02;
if SIG_A = SIG_B then -- just 2 signals
fsm_state <= STATE_01;
end if;
Click to expand...
should be equivalent to the above, but safer if there is any doubt about
the equality test.

But most likely, your synthesis tool doesn't know how to generate an
equality test between two signals, only between a single signal and a
known value, like "Sig_A = '1'"

In which case, note that "SIG_A = SIG_B" is equivalent to
"(Sig_A XOR SIG_B) = '0'", which SHOULD be recognisable by any synthesis
tool.

- Brian
 
Charlie" <Charlie@no_spam.com> wrote in message
news:bsl33v$5t5$1@news7.svr.pol.co.uk...
Hello,

I'm trying to code a simple state machine in VHDL. When I simulate it it
seems to run okay, but when I run it for real inside an FPGA it just seems
to get stuck in the first state. The first state has an IF statement in
it,
if I remove this IF statement the FSM runs without getting stuck. The
following shows how I have coded the FSM:

state_machine : process(RST, FAST_CLK)
begin
if RST = '0' then
fsm_state <= IDLE;
elsif FAST_CLK'event and FAST_CLK = '1' then
case fsm_state is
when IDLE =
fsm_state <= STATE_00;

when STATE_00 =
if SIG_A = SIG_B then -- just 2 signals
fsm_state <= STATE_01;
else
fsm_state <= STATE_02;
end if;

when STATE_01 =
.
.
.

When I run the code in the FPGA it just gets stuck in STATE_00. FAST_CLK
is
definatley running (I can see it on an oscilliscope) and the RST signal is
equal to 1. I know it's stuck in STATE_00 because I make the FPGA turn on
certain signals in certain states, I then watch the signals on a logic
analyzer. If I remove the IF statement and replace it with either
'fsm_state <= STATE_01' or 'fsm_state <= STATE_02' the fsm runs okay.

So, does anyone have any idea on what I'm doing wrong? I'm using the
XILINX
ISE software. If anyone needs any further details then just let me know.

Thanks for any advice,
Click to expand...
I've been doing some more searching on the Internet and it looks like the
problem might be to do with crossing clock domains. Does this sound right?

My FSM is a simple PLL (used to extract a clock from a signal), it has an
input clock of 5MHz and the encoded data signal runs at about 500KHz. Do I
need to synchronise the input clock and the input encoded signal? How would
I do this?
 
I am not sure what's the problem too.

But I would prefer to implement the state machine using 2 processes
style, one for combinational process and one for sequential process.
This would help me to figure out the operations easily.

Perhaps this is my humble opinion. :)
 
"Wong" <tatto0_2000@yahoo.com> wrote in message
news:509bfe22.0312281626.4fbec99c@posting.google.com...
I am not sure what's the problem too.

But I would prefer to implement the state machine using 2 processes
style, one for combinational process and one for sequential process.
This would help me to figure out the operations easily.

Perhaps this is my humble opinion. :)
Click to expand...

Thanks for your replies.

I've synchronised (I think I spelt that wrong) the two clocks and now the
FSM works as it should.
 
"Charlie" <Charlie@no_spam.com> wrote in message news:<bsmpab$ldo$1@news5.svr.pol.co.uk>...
Charlie" <Charlie@no_spam.com> wrote in message
news:bsl33v$5t5$1@news7.svr.pol.co.uk...
Hello,

I'm trying to code a simple state machine in VHDL. When I simulate it it
seems to run okay, but when I run it for real inside an FPGA it just seems
to get stuck in the first state. The first state has an IF statement in
it,
if I remove this IF statement the FSM runs without getting stuck. The
following shows how I have coded the FSM:

state_machine : process(RST, FAST_CLK)
begin
if RST = '0' then
fsm_state <= IDLE;
elsif FAST_CLK'event and FAST_CLK = '1' then
case fsm_state is
when IDLE =
fsm_state <= STATE_00;

when STATE_00 =
if SIG_A = SIG_B then -- just 2 signals
fsm_state <= STATE_01;
else
fsm_state <= STATE_02;
end if;

when STATE_01 =
.
.
.

When I run the code in the FPGA it just gets stuck in STATE_00. FAST_CLK
is
definatley running (I can see it on an oscilliscope) and the RST signal is
equal to 1. I know it's stuck in STATE_00 because I make the FPGA turn on
certain signals in certain states, I then watch the signals on a logic
analyzer. If I remove the IF statement and replace it with either
'fsm_state <= STATE_01' or 'fsm_state <= STATE_02' the fsm runs okay.

So, does anyone have any idea on what I'm doing wrong? I'm using the
XILINX
ISE software. If anyone needs any further details then just let me know.

Thanks for any advice,





I've been doing some more searching on the Internet and it looks like the
problem might be to do with crossing clock domains. Does this sound right?

My FSM is a simple PLL (used to extract a clock from a signal), it has an
input clock of 5MHz and the encoded data signal runs at about 500KHz. Do I
need to synchronise the input clock and the input encoded signal? How would
I do this?
Click to expand...
Charlie

The typical way is to feed the signal to be synchronized into a d
flip-flop. Feed that flip-flop's output into a second d flip-flop.
Use the second flip-flop's output in your state machine. Both
flip-flops are clocked with the state machine clock. I use this
technique so often that I have made a synchronizer component and put
it in a library. If you don't know how to make a d flip-flop, let me
know.

Charles
 
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