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Eric
Guest
Hi guys, im trying to synthasize an FSM into a Xilinx Spartan-3 and
keep getting problems with IOB usage....here is part of the report:
Design Statistics
# IOs : 263
Cell Usage :
# BELS : 135
# LUT2 : 132
# LUT3 : 3
# FlipFlops/Latches : 134
# FDC : 3
# FDP : 1
# LD_1 : 130
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 261
# IBUF : 131
# OBUF : 130
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200tq144-4
Number of Slices: 78 out of 1920 4%
Number of Slice Flip Flops: 134 out of 3840 3%
Number of 4 input LUTs: 135 out of 3840 3%
Number of bonded IOBs: 261 out of 97 269% (*)
Number of GCLKs: 1 out of 8 12%
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
Im a begginer to synthesis so im not sure if this is a problem with my
coding style or synthesis settings. Would appreaciate any tips. Thanks
Eric
keep getting problems with IOB usage....here is part of the report:
Design Statistics
# IOs : 263
Cell Usage :
# BELS : 135
# LUT2 : 132
# LUT3 : 3
# FlipFlops/Latches : 134
# FDC : 3
# FDP : 1
# LD_1 : 130
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 261
# IBUF : 131
# OBUF : 130
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s200tq144-4
Number of Slices: 78 out of 1920 4%
Number of Slice Flip Flops: 134 out of 3840 3%
Number of 4 input LUTs: 135 out of 3840 3%
Number of bonded IOBs: 261 out of 97 269% (*)
Number of GCLKs: 1 out of 8 12%
WARNING:Xst:1336 - (*) More than 100% of Device resources are used
Im a begginer to synthesis so im not sure if this is a problem with my
coding style or synthesis settings. Would appreaciate any tips. Thanks
Eric