FSM going crazy

[Timo Gerber]

Hi,
i hve a huge problem with my FSM. It's the implentation of an
transmitting module with handshake signals:
I try to transfer 3 data_blocks which are registered in a seperate process.
The problem occurs in state "block2"
In the sim, the valid signal is assigen, while the output signal is not
changing, although they are assigned at the same time.


PROCESS (clk, areset)
BEGIN
IF areset = '0' THEN

state <= idle;

ELSIF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN idle => test_state <= 0;
valid <= '0';
IF start = '1' AND accept = '0' THEN
valid <= '1';
output <= data_block1;
state <= block1; ELSE
state <= idle;
END IF;

WHEN block1 => test_state <= 1;
IF accept = '0' THEN
state <= block1;
ELSIF accept = '1' THEN
state <= block1_wait;
valid <= '0';
output(13 downto 0) <= (OTHERS => '0');
END IF;

WHEN block1_wait => test_state <= 2;
IF accept = '0' THEN
state <= block2;
valid <= '1';
output <= data_block2;
ELSE
state <= block1_wait;
END IF;
WHEN block2 =>
test_state <= 3;
IF accept = '0' THEN
state <= block2;
ELSIF accept = '1' THEN
valid <= '0';
output(13 downto 0) <= (OTHERS => '0');
state <= block2_wait;
END IF;
WHEN block2_wait => test_state <= 4;
IF accept = '0' THEN
valid <= '1';
output <= data_block3;
state <= block3;
ELSE
state <= block2_wait;
END IF;

WHEN block3 => test_state <= 5;
IF accept = '0' THEN
state <= block3;
ELSIF accept = '1' THEN
valid <= '0';
output(13 downto 0) <= (OTHERS => '0'); -- BIG PROBLEM HERE!

state <= block3_wait;
END IF;

WHEN block3_wait => test_state <= 6;
state <= idle;
WHEN OTHERS =>
state <= idle;
END CASE;
END IF;
END PROCESS;

 

[Paul Uiterlinden]

Timo Gerber wrote:

Hi,
i hve a huge problem with my FSM.

Going crazy? Huge problem? BIG PROBLEM HERE!
Why do you act if this is the end of the world?

It's the implentation of an
transmitting module with handshake signals:
I try to transfer 3 data_blocks which are registered in a seperate
process. The problem occurs in state "block2"

Block3?

In the sim, the valid signal is assigen, while the output signal is not
changing, although they are assigned at the same time.

I'm not going to decipher your code, because the (lack of proper)
indentation makes it unreadable.

My advice: set a breakpoint in your code and single step through it. See
that the code that you think is executed is really executed and see whether
the signal assignment is not overwritten by another assignment in the same
clock cycle.

--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.

 

[Ajeetha (www.noveldv.com)]

If you really need help, you should consider giving more information
such as your testbench/testcase and full code. Also did you run a lint
tool on this code?

Ajeetha, CVC
www.noveldv.com