From which memory-deep it is more meaningfully to use a RAM

I am searching for the border when it is meaningfull to use a RAM or
RegisterFile instead of of a RTL register description. Has someone
empirical values when it is better to use RAM hardmacros to save area ?

Thanks calzi

 

[Allan Herriman]

On 7 Mar 2006 23:49:38 -0800, calzinide@yahoo.de wrote:

I am searching for the border when it is meaningfull to use a RAM or
RegisterFile instead of of a RTL register description. Has someone
empirical values when it is better to use RAM hardmacros to save area ?

You don't mention the target architecure.

For Xilinx FPGAs, there is a small 16 location RAM that only uses one
LUT for single port or two LUTs for dual port (r + r/w).
This means it is more efficient in terms of space to use a RAM instead
of flip flops for even the tiniest memories.

For an ASIC, the threshold would be much larger.

Regards,
Allan

 

[Andy]

My experience with FPGAs has indicated that anything above 3x has a
definite benefit in clb ram. Note however, than the latest Virtex4
have only half of their clb luts can be rams, but I doubt that would
make a difference for when it is best to use rams or not. OTOH, if it
takes significant overhead to manage the fact that you only have read
access to one or two "registers" at a time in a ram, then the threshold
may get much higher.

I would also strongly suggest you use your synthesis tool's ability to
infer ram from arrays, rather than instantiating macros for ram, unless
you are using some of the advanced features of block rams that cannot
be inferred from RTL. Inferred rams can store non-std_logic type data,
such as integers, booleans, enums, etc., and are indexed with integers,
both of which make for much faster simulations.

Andy Jones

 

[Mike Treseler]

calzinide@yahoo.de wrote:

I am searching for the border when it is meaningfull to use a RAM or
RegisterFile instead of of a RTL register description. Has someone
empirical values when it is better to use RAM hardmacros to save area ?

I have had no reason to use a vendor macro.
I use a standard blockram template that works
for both brandX and A. For some minimum dimensions, synthesis
makes a block ram, for others I get registers.

-- Mike Treseler