From vhdl to verilog

[mattia]

Hi, can you help me translate this peace of code from vhdl to verilog:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity multi_instance is
generic( N: integer := 3 );
port(
key1_in: in std_logic_vector(0 to 63);
key2_in: in std_logic_vector(0 to 63);
key3_in: in std_logic_vector(0 to 63);
function_select: in std_logic; -- active when
encryption, inactive when decryption

save_out: in std_logic;
serial_data_in: in std_logic;
serial_data_out: out std_logic;

lddata: in std_logic; -- active when
data for loading is ready
ldkey: in std_logic; -- active when
key for loading is ready
out_ready: out std_logic_vector(0 to 2); --
active when encryption of data is done
reset: in std_logic;
clock: in std_logic
);
end multi_instance;

architecture rt of multi_instance is

component tdes_top is
port(
key1_in: in std_logic_vector(0 to
63);
key2_in: in std_logic_vector(0 to
63);
key3_in: in std_logic_vector(0 to
63);
function_select: in std_logic; --
active when encryption, inactive when decryption
data_in: in std_logic_vector(0 to
63);
data_out: out std_logic_vector(0 to
63);
lddata: in
std_logic; -- active when data for loading is ready
ldkey: in
std_logic; -- active when key for loading is ready
out_ready: out
std_logic; -- active when encryption of data is done
reset: in std_logic;
clock: in std_logic
);
end component;

signal sregin: std_logic_vector(0 to 64+N-2);
signal sregout: std_logic_vector(0 to 64*N-1);
signal sout: std_logic_vector(0 to 64*N-1);

begin

process( clock, reset )
begin
if reset = '1' then
sregin <= (others => '0');
sregout <= (others => '0');
else
if clock'event and clock = '1' then
sregin <= serial_data_in & sregin(0 to 64
+N-3);
if save_out = '1' then
sregout <= sout;
else
sregout <= '0' & sregout(0 to
64*N-2);
end if;
end if;
end if;
end process;


UU: for I in 0 to 2 generate
U: tdes_top port map(
key1_in => key1_in,
key2_in => key2_in,
key3_in => key3_in,
function_select => function_select,
data_in => sregin(I to 63+I),
data_out => sout(I*64 to (I+1)*64 - 1),
lddata => lddata,
ldkey => ldkey,
out_ready => out_ready(I),
reset => reset,
clock => clock );
end generate;

serial_data_out <= sregout(64*N-1);

end rt;












--
__mattia__

 

[Jonathan Bromley]

On 14 Dec 2008 11:55:06 GMT, mattia wrote:

Hi, can you help me translate this peace
of code from vhdl to verilog:

It looks as though the code is already buggy. There's
probably a typo in the process (see below) and it is
strange that the generate loop iterates over the
fixed range 0 to 2 rather than 0 to N-1. You may care
to review these issues before introducing further pain
by migrating to Verilog.

The code contains one clocked process and three generated
instances. The clocked process has no variables.
Consequently it is very easy to translate to Verilog.
I'll give you the clocked process for free because
it's so simple (oh, I got rid of the ghastly tabs in
your code text - WHY the blazes do people insist on
using tabs rather than spaces to indent????)

VHDL:
process( clock, reset )
begin
if reset = '1' then
sregin <= (others => '0');
sregout <= (others => '0');
else
if clock'event and clock = '1' then
--------------------- this looks like a typo,
--------------------- probably should be 64*N-3
sregin <= serial_data_in & sregin(0 to 64+N-3);
if save_out = '1' then
sregout <= sout;
else
sregout <= '0' & sregout(0 to 64*N-2);
end if;
end if;
end if;
end process;

Verilog:
always @(posedge clock or posedge reset)
if (reset) begin
sregin <= 0;
sregout <= 0;
end else begin
sregin <= {serial_data_in, sregin[0:64*N-3]};
if (save_out)
sregout <= sout;
else
sregout <= sregout >> 1;
end

The generate loop is also fairly easy:

VHDL:
for i in 0 to 2 generate
....
endgenerate

Verilog:
generate
genvar i;
for (i=0; i<3; i=i+1) // should it be i<N ???
begin : repeated_blocks
////// instances here
end
endgenerate

And the generic on your entity readily maps to
a parameter on your module:

VHDL:
entity multi_instance is
generic (N: integer := 3);
port (... -- port list

Verilog:
module multi_instance
#(parameter N = 3)
(...//port list

In general, translating RTL Verilog into VHDL is trivial
because synthesisable Verilog is a rather limited subset
of synthesisable VHDL. The only problem area I've ever
encountered is the use of casex/casez; these can always
be mimicked easily enough in VHDL, but you may end up
with priority logic whereas the Verilog code may have
had parallel_case directives to encourage the synthesis
tool to do certain dangerous optimizations.

Going the other way, RTL VHDL to Verilog, can be
troublesome if the VHDL writer was any good, because
there are things you can do in synthesisable VHDL
that have no easily coded counterpart in Verilog.
The main issues are likely to be:
- procedural assertions, records, multi-dimensional
arrays and enumeration types, though these were
added by SystemVerilog;
- unconstrained ports and subprogram arguments,
which have no counterpart in any form of Verilog
and can be quite hard to emulate if they have
been used creatively.
Generate statements in VHDL used to be a problem, but
all serious tools now fully support Verilog-2001
generates so that is no longer an issue.

Your code has none of the trouble spots, and is
therefore easy to translate.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
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