S
SanSaurus
Guest
Hello NG!
I'm learning VHDL, but still have to understand how my VHDL-code will
end up as gates and LUTs etc in a FPGA...
I did search google, but all I found was some complex sites describing
how it worked, so I try this NG. Good links which describes the above
for a newbie are highly appreciated!
)
1) Default-values?
I have a signal in my architecture of a entity, which I give a default
value, like this:
signal counter : std_logic_vector(7 downto 0) := (others => '0');
Will this default value be put in the FPGA as well? Or should I code
my architecture as if it could be undefined as default?
Maybe it differ from FPGA to FPGA? I'm using a FPGA from the Spartan
family.
2) What's happening when I synthesize?
Can someone in simple steps describe what is happening when I
synthesize, implement design, generate programming file etc. from my
VHDL-code? That could be cool! (I'm using a free version of Xilinx
ISE, but I guess the terms are general).
3) UCF-files
User Constraints Files are mainly (at least for a beginner like me)
how my pins of my FPGA are connected to the outer world, right? - and
how I attach them to inputs on my entities in my VHDL-code.
4) How is my FPGA "booted"?
Now everything has been put in the FPGA and I power up FPGA. Will it
automatically start with the default values right away? Should I wait
for some time, before my entities starts working as expected? I guess
it takes some times to initialize the FPGA? I guess you will refer me
to the datasheets of the specific FPGA on this... ;o) I want to know
if there are some common things, that you have to consider about this
issue.)
--
SanSaurus
I'm learning VHDL, but still have to understand how my VHDL-code will
end up as gates and LUTs etc in a FPGA...
I did search google, but all I found was some complex sites describing
how it worked, so I try this NG. Good links which describes the above
for a newbie are highly appreciated!
)1) Default-values?
I have a signal in my architecture of a entity, which I give a default
value, like this:
signal counter : std_logic_vector(7 downto 0) := (others => '0');
Will this default value be put in the FPGA as well? Or should I code
my architecture as if it could be undefined as default?
Maybe it differ from FPGA to FPGA? I'm using a FPGA from the Spartan
family.
2) What's happening when I synthesize?
Can someone in simple steps describe what is happening when I
synthesize, implement design, generate programming file etc. from my
VHDL-code? That could be cool! (I'm using a free version of Xilinx
ISE, but I guess the terms are general).
3) UCF-files
User Constraints Files are mainly (at least for a beginner like me)
how my pins of my FPGA are connected to the outer world, right? - and
how I attach them to inputs on my entities in my VHDL-code.
4) How is my FPGA "booted"?
Now everything has been put in the FPGA and I power up FPGA. Will it
automatically start with the default values right away? Should I wait
for some time, before my entities starts working as expected? I guess
it takes some times to initialize the FPGA? I guess you will refer me
to the datasheets of the specific FPGA on this... ;o) I want to know
if there are some common things, that you have to consider about this
issue.
)--
SanSaurus