From Java code to Verilog?

Hi,

I'm trying to write a small java program that is capable of producing Verilog code. As I hardly know the Verilog language, I have problems creating a simple example.

Let's assume we have 2 inputs a, b, and 1 output c. Also 2 states. State1 is the initial state, and goes to State2 for a certain condition wire1, which requires b = 1.

My output in this example would have state2 & a as condition to be met.

Question: Using the approximate design below, how would the full Verilog code look according to my example?

//simplified without inheritance
class Input {
String varname;
new Input(String varname);
}

class Output {
String varname;
String condition;
new Output(String varname, String condition);
}

class State {
String varname;
new State(String varname);
}

class Wire {
String condition;
Input input;
Ouput output;
new Wire(Input input, Output output, String condition);
}

Input input1 = new Input("a");
Input input2 = new Input("b");
State state1 = new State("initial");
State state2 = new State("following");
Wire wire12 = new Wire(state1, state2, "b");
Ouput output1 = new Output(c, "state2 & a");

How would the verilog code have to look based on this?

module BasicFsm(
input clock,
input reset,
input a,
input b,
output c
);

always @(posedge clock)
//how to continue here?

 

[unfrostedpoptart]

On Tuesday, April 9, 2013 6:55:38 AM UTC-7, kodyr...@gmail.com wrote:

Hi,

I'm trying to write a small java program that is capable of producing Verilog code. As I hardly know the Verilog language, I have problems creating a simple example.

How can you possibly do this if you don't know Verilog? Your question is Verilog 101 and explained in dozens of book and websites. You want someone here to teach you the language? It sounds like a complicated project (basically a pre-processor) that requires a lot of knowledge of Verilog.

David

 

[garyr]

Forget Java, try Python: www.myhdl.org/doku.php