From ASIC to FPGA these days

[avalanche effect]

Googling web & usenet didn't provide answer or pointers - so here it
goes:

We have a fully tested design on fat Xilinx FPGA. Must go to ASIC,
0.18 or better. Relatively simple design, 3 clock domains, 300K gates.
The only interface is USB, so very low pin count. If the foundry
doesn't have USB phy in standard lib, we'll interface external phy.

The question is - how long does it take - how many months ? We will
farm that out, but I need some realistic idea about time between
giving cash and working FPGA code to this outsourcing entity until we
get first chips in sample quantities.

I fully understand that each project is different, but feel
uncomfortable with sales' quotes - I'd like to hear real experiences.

And, BTW, are fabs busy these days or are they in mood for deals ?

 

[Jon Beniston]

The question is - how long does it take - how many months ? We will
farm that out, but I need some realistic idea about time between
giving cash and working FPGA code to this outsourcing entity until we
get first chips in sample quantities.

Give your design house a month, and the fab 6-8 weeks.

Cheers,
Jon

 

[avalanche effect]

Just changing the Subject: to what is should have been ...

Googling web & usenet didn't provide answer or pointers - so here it
goes:

We have a fully tested design on fat Xilinx FPGA. Must go to ASIC,
0.18 or better. Relatively simple design, 3 clock domains, 300K gates.
The only interface is USB, so very low pin count. If the foundry
doesn't have USB phy in standard lib, we'll interface external phy.

The question is - how long does it take - how many months ? We will
farm that out, but I need some realistic idea about time between
giving cash and working FPGA code to this outsourcing entity until we
get first chips in sample quantities.

I fully understand that each project is different, but feel
uncomfortable with sales' quotes - I'd like to hear real experiences.

And, BTW, are fabs busy these days or are they in mood for deals ?

 

[john jakson]

unexpectedvalue@yahoo.com (avalanche effect) wrote in message news:<1dcb9a53.0312170953.1b9e2e6c@posting.google.com>...

Just changing the Subject: to what is should have been ...



Googling web & usenet didn't provide answer or pointers - so here it
goes:

We have a fully tested design on fat Xilinx FPGA. Must go to ASIC,
0.18 or better. Relatively simple design, 3 clock domains, 300K gates.
The only interface is USB, so very low pin count. If the foundry
doesn't have USB phy in standard lib, we'll interface external phy.

The question is - how long does it take - how many months ? We will
farm that out, but I need some realistic idea about time between
giving cash and working FPGA code to this outsourcing entity until we
get first chips in sample quantities.

I fully understand that each project is different, but feel
uncomfortable with sales' quotes - I'd like to hear real experiences.

And, BTW, are fabs busy these days or are they in mood for deals ?

Check out Lightspeed and Flextronics. Lightspeed has a good story on
their website clearly chasing after Xilinx architectures but I have no
personal experience of either (yet). Apart from block rams, the IP is
the big gotcha here. Lightspeed only customizes 2 layers of metal so
it should be quick.

johnjaksonATusaDOTcom

 

[Ulf Samuelsson]

"avalanche effect" <unexpectedvalue@yahoo.com> wrote in message
news:1dcb9a53.0312161905.6c373e24@posting.google.com...

Googling web & usenet didn't provide answer or pointers - so here it
goes:

We have a fully tested design on fat Xilinx FPGA. Must go to ASIC,
0.18 or better. Relatively simple design, 3 clock domains, 300K gates.
The only interface is USB, so very low pin count. If the foundry
doesn't have USB phy in standard lib, we'll interface external phy.

The question is - how long does it take - how many months ? We will
farm that out, but I need some realistic idea about time between
giving cash and working FPGA code to this outsourcing entity until we
get first chips in sample quantities.

I fully understand that each project is different, but feel
uncomfortable with sales' quotes - I'd like to hear real experiences.

And, BTW, are fabs busy these days or are they in mood for deals ?

If you send me Your contact information in a mail,
I can provide you with a contact to Atmels ULC offering.
Assuming you have a good business case (enough volume),
then Atmel can take your complete design + test vectors and design the ASIC.
I belive that there will not be any need to go to an external design house
for this.
Atmel delivers many ASICs with built in USB phy so this will not be a
problem.
My guess is that it should take 4-6 months.


--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

 

[Vaughn Betz]

Googling web & usenet didn't provide answer or pointers - so here it
goes:

We have a fully tested design on fat Xilinx FPGA. Must go to ASIC,
0.18 or better. Relatively simple design, 3 clock domains, 300K gates.
The only interface is USB, so very low pin count. If the foundry
doesn't have USB phy in standard lib, we'll interface external phy.

The question is - how long does it take - how many months ? We will
farm that out, but I need some realistic idea about time between
giving cash and working FPGA code to this outsourcing entity until we
get first chips in sample quantities.

I fully understand that each project is different, but feel
uncomfortable with sales' quotes - I'd like to hear real experiences.

And, BTW, are fabs busy these days or are they in mood for deals ?

One option for a low-risk ASIC conversion is to convert the design to
Stratix, then use Altera's HardCopy conversion to an ASIC. It does
mean you have to do an FPGA conversion, but that's easy to test
immediately because you can try the FPGA right away. Then the ASIC
conversion (HardCopy) is relatively easy, since you use the same
synthesis & placement tools as you did for the FPGA, and all the
tricky IP blocks like RAMs are the same in the HardCopy array as they
are in the FPGA.

So it's a two-step conversion process, but it lowers your risk.

Vaughn
Altera