frequency synthesizer basics

[Lost'n Found]

Hello,

I was reading about frequency synthesizers and it seems I am missing some
concept.

These synthesizers can generate higher frequency. On the specification
sheets, I read that we can divide the reference frequency by certain
factors. My question is: If we are dividing the frequency, why are we
getting much higher frequencies at the output?

 

[werty]

Phase Locked Loops PLL

VCO voltage controlled oscillator is controlled from a much lower freq
,

This OSC is divided down so it can be compared to a Crystal CLOCK .


OSC is 50 MegaHrtz , divided down 100 times to .5 Mhz .
a Crystal OSC REF at same .5mhz is compared , and any phase
difference
produces a DC error voltage . This DC is sent up to the 50 mhz VCO .
Say the error DC is an increase of .1 volts and VCO jumps 1 mhz ,

They call it "gain" , which is 1mhz/.1 or 10mz per volt .
But VCO has trouble stopping at any freq you like , it can only
step by 1/2 megahertz .!
So special chips do a complicated "divide down" and get more steps
finer adjustment ..

Dual modulus prescalers simply count down on one divider and when it
figures it's at right place , starts couning down in the other divider
..

Phase jitter can be a problem , so if you filter the DC more , you
nix jitter
but slow the responce , so now your Radio Shack scanner hops very slow
!
They have secrets to remove jitter .

Freq Counters use PLL to improve the rading but also to put back in
what the signal dropped . If signal is unreliable and it drops
a bit , the PLL will simply add that missing bit to the freq counter
and you'll get a good reading MPD Missing Pulse detectors...






Lost'n Found wrote:

Hello,

I was reading about frequency synthesizers and it seems I am missing some
concept.

These synthesizers can generate higher frequency. On the specification
sheets, I read that we can divide the reference frequency by certain
factors. My question is: If we are dividing the frequency, why are we
getting much higher frequencies at the output?