Frequency Doubler - VHDL/Verilog

G

Gazelle

Guest
Good day gents,
I am wondering if VHDL (or Verilog) code exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric duty cycle.
Below some code can be found which generates a by-2 multiplied frequency - however the duty cycle
is very assymmetrical ...

Many thanks for your input !

Regards,

Michel


-- Frequency Doubler using DFF
-- code in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo = 2*fi
end F2;


architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;


begin
process (clk) begin
if (clk 'event and clk = '1') then
q <= notq;
end if;
end process;

notq <= not q ;
clk <= (notq xnor fi) ;
fo <= clk;

end behav;
 
You can't make a symmetric-duty-cycle frequency doubler in digital logic unless you have a precisely controlled delay element.
-Kevin
"Gazelle" <wmu@pandora.be> wrote in message news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be...
Good day gents,
I am wondering if VHDL (or Verilog) code exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric duty cycle.
Below some code can be found which generates a by-2 multiplied frequency - however the duty cycle
is very assymmetrical ...

Many thanks for your input !

Regards,

Michel


-- Frequency Doubler using DFF
-- code in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo = 2*fi
end F2;


architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;


begin
process (clk) begin
if (clk 'event and clk = '1') then
q <= notq;
end if;
end process;

notq <= not q ;
clk <= (notq xnor fi) ;
fo <= clk;

end behav;
 
If you don't care about the 2f duty cycle, and are also willing to live
with the affect of uncontrolled incoming duty cycle at f, causing
alternating period length at 2f, then you can use the circuit described
in TechXclusives "Six Easy Pieces".
But if you need better defined timing, you need a DLL- or PLL-like
structure, there is no way around that.
Peter Alfke, Xilinx Applications
================
Gazelle wrote:

Good day gents,
I am wondering if VHDL (or Verilog) code
exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric
duty cycle.
Below some code can be found which generates a by-2 multiplied
frequency - however the duty cycle
is very assymmetrical ...

Many thanks for your input !

Regards,

Michel


-- Frequency Doubler using DFF
-- code in VHDL
library ieee;
use ieee.std_logic_1164.all;

entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo = 2*fi
end F2;


architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;


begin
process (clk) begin
if (clk 'event and clk = '1') then
q <= notq;
end if;
end process;

notq <= not q ;
clk <= (notq xnor fi) ;
fo <= clk;

end behav;
Click to expand...
 
If you don't care about the 2f duty cycle, and are also willing to live
with the affect of uncontrolled incoming duty cycle at f, causing
alternating period length at 2f, then you can use the circuit described
in TechXclusives "Six Easy Pieces".
Click to expand...
Assuming the clock is always running and at least in the ballpark of
50-50 duty cycle...

Can I fixup the duty cycle with a cap, inverter, and big
feedback/bias resistor?

If I'm willing to go off-chip and back in, will that work for the
2F clock?

[Yes, DLLs/PLLs are good.]

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
Hal,
I like your line or thought, and I have been thinking along the same
lines, without good results.
Maybe this community can come up with a simple solution:
Use a few external components to adjust the duty cycle, and perhaps also
the alternate period problem.
For simplicity: accept a relatively low frequency ( <40 MHz).
Any takers out there?
I can promise publication, fame and glory...
Peter Alfke
==============================
Hal Murray wrote:
If you don't care about the 2f duty cycle, and are also willing to live
with the affect of uncontrolled incoming duty cycle at f, causing
alternating period length at 2f, then you can use the circuit described
in TechXclusives "Six Easy Pieces".

Assuming the clock is always running and at least in the ballpark of
50-50 duty cycle...

Can I fixup the duty cycle with a cap, inverter, and big
feedback/bias resistor?

If I'm willing to go off-chip and back in, will that work for the
2F clock?

[Yes, DLLs/PLLs are good.]

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Click to expand...
 
HI,
You didn't say anything about the frequency, so maybe for lower frequencies one way is to cascade 2 of these 2f circuits to get a 4f frequency and then using a simple flipflop to divide it by two, get a perfect 50% duty cycle 2f signal.

Best Regards
Arash
"Gazelle" <wmu@pandora.be> wrote in message news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be...
Good day gents,
I am wondering if VHDL (or Verilog) code exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric duty cycle.
Below some code can be found which generates a by-2 multiplied frequency - however the duty cycle
is very assymmetrical ...

Many thanks for your input !

Regards,

Michel


-- Frequency Doubler using DFF
-- code in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo = 2*fi
end F2;


architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;


begin
process (clk) begin
if (clk 'event and clk = '1') then
q <= notq;
end if;
end process;

notq <= not q ;
clk <= (notq xnor fi) ;
fo <= clk;

end behav;
 
Arash,
That won't work. Try drawing a timing diagram to see why!
cheers, Syms.

"Arash Salarian" <arash dot salarian at epfl dot ch> wrote in message
news:3fb3a9cf$1@epflnews.epfl.ch...
HI,
You didn't say anything about the frequency, so maybe for lower frequencies
one way is to cascade 2 of these 2f circuits to get a 4f frequency and then
using a simple flipflop to divide it by two, get a perfect 50% duty cycle 2f
signal.

Best Regards
Arash
"Gazelle" <wmu@pandora.be> wrote in message
news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be...
Good day gents,
I am wondering if VHDL (or Verilog) code exists in
order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric duty
cycle.
Below some code can be found which generates a by-2 multiplied frequency -
however the duty cycle
is very assymmetrical ...

Many thanks for your input !

Regards,

Michel
 
Doubling again and then dividing does not solve the problem. It just
gets you back where you were. :-(
Peter Alfke
 
On a sunny day (Wed, 12 Nov 2003 13:55:30 -0800) it happened Peter Alfke
<peter@xilinx.com> wrote in <3FB2AC53.76A5CA48@xilinx.com>:

Hal,
I like your line or thought, and I have been thinking along the same
lines, without good results.
Maybe this community can come up with a simple solution:
Use a few external components to adjust the duty cycle, and perhaps also
the alternate period problem.
For simplicity: accept a relatively low frequency ( <40 MHz).
Any takers out there?
I can promise publication, fame and glory...
Peter Alfke
Well, the analog way was to make a coil with a center tap and 2 diodes.
Click to expand...
The double phase rectified wave you get is 2f ( like 120 Hz hum from 60 Hz
supply).
This works fine for analog (amplitude modulated) signals too, I have used it
a 4.43 MHz to double color subcarrier.
You will have to go off FPGA, drive a small ferrite transformer, slice it with a
transistor, and back into FPGA.
In these days many people are paranoid about discrete components perhaps.
Not to mention a coil or transformer.
But it is really simple.
Of cause any non-linear component (MOSFET / FET / Transistor) can be used
to double frequency, just bias it in the non linear region, and put a circuit tuned to
2f in its output, 3 f and 4f also works fine.
Radio stuff.
 
Well, this only works with a tuned circuit that filters out the subharmonics.
The issue with a truly digital internal solution is the sensitivity to
incoming non-50% duty cycle. No transformer and rectifier alone can help
there, but a tuned circuit would. But LCs are not so fashionable anymore...
Peter Alfke

Jan Panteltje wrote:
On a sunny day (Wed, 12 Nov 2003 13:55:30 -0800) it happened Peter Alfke
peter@xilinx.com> wrote in <3FB2AC53.76A5CA48@xilinx.com>:

Hal,
I like your line or thought, and I have been thinking along the same
lines, without good results.
Maybe this community can come up with a simple solution:
Use a few external components to adjust the duty cycle, and perhaps also
the alternate period problem.
For simplicity: accept a relatively low frequency ( <40 MHz).
Any takers out there?
I can promise publication, fame and glory...
Peter Alfke
Well, the analog way was to make a coil with a center tap and 2 diodes.
The double phase rectified wave you get is 2f ( like 120 Hz hum from 60 Hz
supply).
This works fine for analog (amplitude modulated) signals too, I have used it
a 4.43 MHz to double color subcarrier.
You will have to go off FPGA, drive a small ferrite transformer, slice it with a
transistor, and back into FPGA.
In these days many people are paranoid about discrete components perhaps.
Not to mention a coil or transformer.
But it is really simple.
Of cause any non-linear component (MOSFET / FET / Transistor) can be used
to double frequency, just bias it in the non linear region, and put a circuit tuned to
2f in its output, 3 f and 4f also works fine.
Radio stuff.
Click to expand...
 
Gazelle wrote:
Good day gents,
I am wondering if VHDL (or Verilog) code
exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric
duty cycle.
Below some code can be found which generates a by-2 multiplied
frequency - however the duty cycle
is very assymmetrical ...
Click to expand...
If you think about this, you are asking for 'clairvoyant logic'
- it has to know where to put the extra edges, in order to give
symmetric output.
You CAN double Freq, to get an OP positive edge for each IP edge,
but the OP falling edge has no IP info to relate to, so is
device delay determined.

So, you will need some analog interpolation scheme - that can be :
- Accept fixed freq operation, and design appx delays as nominal 50%
- RC integrator & comparitor, to give quadrature signals which can
then be doubled to close to 50%.
- narrow band tuned circuit, ringing at target 2f
- Full PLL approach

-jg
 
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