frequency doubler in Altera CPLD

[anupam]

Hi Guys,
Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.
Thanx in advance .
Regards,
anup

 

[Mike Treseler]

anupam wrote:

Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.

The EPM3064 has no PLL clock generator.
Consider using an fpga that has one,
or add one of these to your board:
http://www.google.com/search?q=PLL+programmable+clock+generator

-- Mike Treseler

 

[john]

Hi,

I do not think so that u can do frequency doubling!

Regards
john

"anupam" <anupam@coraltele.com> wrote in message news:<309d5f7dcfa6feb4e473c8c414a24472@localhost.talkaboutprogramming.com>...

Hi Guys,
Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.
Thanx in advance .
Regards,
anup

 

[Hal Murray]

anupam wrote:

Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.

The EPM3064 has no PLL clock generator.

It's possible but very kludgy to do clock doubling by using
an XOR gate. The doubled clock clocks a FF and the output
of that FF goes to the XOR. That way you know the clock pulse
is wide enough to clock a FF.

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[john]

Hi again,

you might want to look into Phase lock Loops ( PLL)...

Bye
John

"anupam" <anupam@coraltele.com> wrote in message news:<309d5f7dcfa6feb4e473c8c414a24472@localhost.talkaboutprogramming.com>...

Hi Guys,
Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.
Thanx in advance .
Regards,
anup

 

[Leon Heller]

"anupam" <anupam@coraltele.com> wrote in message
news:309d5f7dcfa6feb4e473c8c414a24472@localhost.talkaboutprogramming.com...

Hi Guys,
Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.

Best do it with an actual RF 'doubler' - a couple of diodes and a wideband
balun transformer - followed by an LP filter and simple amplifier stage.

Leon

 

[Eric Smith]

"anupam" <anupam@coraltele.com> writes:

Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.

Maybe the technique in section 4 of "Six Easy Pieces (Non-Synchronous
Circuit Tricks)", a Xilinx TechXclusive by Peter Alfke, might be usable?

 

[Ken Smith]

In article <419d8e62$0$1821$cc9e4d1f@news-text.dial.pipex.com>,
Leon Heller <leon_heller@hotmail.com> wrote:

"anupam" <anupam@coraltele.com> wrote in message
news:309d5f7dcfa6feb4e473c8c414a24472@localhost.talkaboutprogramming.com...
Hi Guys,
Can anybody help me to develope a frequency doubler in Altera CPLD
EPM3064ATC100-10. Input freq is 50 Mhz and o/p reqd is 100 Mhz.

Best do it with an actual RF 'doubler' - a couple of diodes and a wideband
balun transformer - followed by an LP filter and simple amplifier stage.

If you are doing it the RF way you need to:

(1)
Band pass filter to remove the DC and the harmonics.

(2)
Double with a Schottky diode or the like.

(3)
Band pass filter to extract just the 100MHz.

This is a lot of electronics.


Chances are it would be simpler to make a 100MHz crystal oscillator. If
the 100MHz really has to be twice the 50MHz (ie: the errors must track)
you can sync the 100MHz crystal to the 50MHz by coupling in a small spike.

--
--
kensmith@rahul.net forging knowledge