frequency divider

[Gandalf]

Hi,
i need a frequency divider for the clock.
The Virtex fpga has a clock of 50MHz i need a clock of 1MHz.
can somebody help me?

some VHDL script?

thank u

 

[Gandalf]

i'm don't know the "obvious divide-by-50 - counter"

can u write me the code please?

 

[Ralf Hildebrandt]

Gandalf wrote:

i'm don't know the "obvious divide-by-50 - counter"

Count with every rising edge of your input clock till 25, then invert a
flipflop. Do it infinitely. Remember, that your output flipflop has to
be reseted.

I strongly suggest reading a VHDL book. This is a very basic task. If
you can't solve it, you will have serious problems with more complex tasks.

Ralf

 

[Gandalf]

architecture divisore_body of divisore is
signal count: integer range 0 to 50;

begin
process(clk_in)

begin

if rising_edge(clk_in) then
if (count<25) then
clk_out <= '1';
count<= count+1;
elsif (count>=25 and count<50) then
clk_out<='0';
count <= count+ 1;
elsif (count=50) then
clk_out<='1';
count<=1;
end if;
end if;

end process;
end divisore_body

---------------------------------

what do u think?

 

[Ralf Hildebrandt]

Gandalf wrote:

architecture divisore_body of divisore is
signal count: integer range 0 to 50;

begin
process(clk_in)

begin

if rising_edge(clk_in) then
if (count<25) then
clk_out <= '1';
count<= count+1;
elsif (count>=25 and count<50) then
clk_out<='0';
count <= count+ 1;
elsif (count=50) then
clk_out<='1';
count<=1;
end if;
end if;

end process;
end divisore_body

---------------------------------

what do u think?

Too much overhead ;-) but the right idea. You forgot a reset.

process(reset,clk)
begin
if (reset='0') then
count<=0;
clk_out<='0';
elsif rising_edge(clk) then
if (count=24) then -- 0 to 24 = 25 clocks
clk_out<=NOT(clk_out);
count<=0;
else
count<=count+1;
end if;
end if;
end process;


Note that you should feed clk_out via global nets. Otherwise you will
have a lot of clock skew.
Note also, that your FPGA may provide special components for frequency
synthesis / division.

Ralf

 

[Ralf Hildebrandt]

Gandalf wrote:

The Virtex fpga has a clock of 50MHz i need a clock of 1MHz.

What about the obvious divide-by-50 - counter? (Count to 25, invert output.)

Maybe your FPGA offers a specialized frequency divider.

Note, that the divided clock should be routed via a global clock net.

Ralf