frequency divider

[bharathi]

hi all,
i did a module for frequency divider , is capable to convert 30Mhz
to 400 kHz
i can get the proper simulation result, but the code is not
synthesisable, i given the code below.. suggest me some thing


module fre_div (
out_clk,
in_clk,
i_sysrst
);

input in_clk;
input i_sysrst;

output out_clk;

reg out_clk;

reg [6:0]cnt;
reg temp;

always @(posedge in_clk or i_sysrst)
begin
if(!i_sysrst)
begin
cnt <= 7'd0;
out_clk <= 1'b0;
end

else if (cnt == 7'd37)
begin
temp <= 1'b1;
cnt <= cnt +7'd1;
end

else if (cnt == 7'd75)
begin
out_clk <= ~out_clk;
cnt <= 7'd1;
end

else
cnt = cnt+7'd1;
end

always @(negedge in_clk)
begin
if(temp == 1'b1)
begin
out_clk <= ~out_clk;
temp <= 1'b0;
end

end

endmodule

 

[john hong]

This is one of the pitfalls for people new to HDL's. Both temp and
out_clk have two drivers in this code, which would be sythesized to
wired 'OR's using Synopsys DC. For VHDL, it is not even synthesizable
in DC last time I checked...

 

above RTL will give u a race condition..

I pasted correct code at :

http://groups-beta.google.com/group/RTL-SYNTHESIS/browse_thread/thread/28b034fffaec8080
-Ankur

 

above RTL will give u a race condition..

I pasted correct code at :

http://groups-beta.google.com/group/RTL-SYNTHESIS/browse_thread/thread/28b034fffaec8080
-Ankur

 

[Mike Lewis]

You are trying to clock "out_clk" with both a positive and
negative edge of "in_clk". I haven't seen a real life flip yet
that has two clock inputs! That would be one reason why
it's not synthesizable.

Mike



"bharathi" <bharathiii@rediffmail.com> wrote in message
news:22aa3c17.0411250637.327afd3e@posting.google.com...

hi all,
i did a module for frequency divider , is capable to convert 30Mhz
to 400 kHz
i can get the proper simulation result, but the code is not
synthesisable, i given the code below.. suggest me some thing


module fre_div (
out_clk,
in_clk,
i_sysrst
);

input in_clk;
input i_sysrst;

output out_clk;

reg out_clk;

reg [6:0]cnt;
reg temp;

always @(posedge in_clk or i_sysrst)
begin
if(!i_sysrst)
begin
cnt <= 7'd0;
out_clk <= 1'b0;
end

else if (cnt == 7'd37)
begin
temp <= 1'b1;
cnt <= cnt +7'd1;
end

else if (cnt == 7'd75)
begin
out_clk <= ~out_clk;
cnt <= 7'd1;
end

else
cnt = cnt+7'd1;
end

always @(negedge in_clk)
begin
if(temp == 1'b1)
begin
out_clk <= ~out_clk;
temp <= 1'b0;
end

end

endmodule

 

Below is the freq divider by 4 code, whcih is synthesizable, with asyn
reset.

You can modify it to suit ur requirements.
--------------------------------------------------------------------

module FreqDivider1(in_clk, out_clk, _rst);
input in_clk;
input _rst;

output out_clk;

reg out_clk;
reg [6:0] cnt;

always @(negedge _rst)
begin
out_clk <= 1'b0;
cnt <= 0;
end



always @(posedge in_clk)
begin
if (cnt == 1)
begin
out_clk <= ~out_clk;
cnt <= 0;
end
else
cnt <= cnt +1;
end

endmodule
----------------------------------------------------------------

`timescale 1ns/1ns

module newBench ;
reg in_clk;
wire out_clk;

reg _rst;

FreqDivider1 Test_Entity( in_clk, out_clk, _rst);

initial
begin
_rst = 1;
in_clk = 0;
$display( $time," in_clk = %b , out_clk = %b , _rst = %b
",in_clk,out_clk,_rst);
#1 _rst = 0;
$display( $time," in_clk = %b , out_clk = %b , _rst = %b
",in_clk,out_clk,_rst);
#1 _rst = 1;
$display( $time," in_clk = %b , out_clk = %b , _rst = %b
",in_clk,out_clk,_rst);
#8 in_clk = ~in_clk;
$display( $time," in_clk = %b , out_clk = %b , _rst = %b
",in_clk,out_clk,_rst);
forever
begin
#10 in_clk = ~in_clk;
$display( $time," in_clk = %b , out_clk = %b , _rst = %b
",in_clk,out_clk,_rst);
end
end

initial
#300 $finish;

endmodule
------------------------------------------------------------
hope it helps.

-Ankur