Frequency Divider (by 2)

[Chloe]

Hello everyone,

I'm very new to Verilog and hardware design, so any help or advice
given would be appreciated.

I have 2 clocks in my design. First clock is running at 60MHz, and the
other one is generated at a divided frequency of 2 from the first
clock, ie at 30MHz. Because its frequency is only divided by two, I
don't see the need for a counter. But please check and let me know if
I'm thinking wrongly:

-----------------

module FreqDivider(in_clk, out_clk, rst);
input in_clk;
input rst;

output out_clk;
reg out_clk;

always @(posedge in_clk or negedge rst)
begin
if (!rst)
begin
out_clk <= 1'b0;
end
else
out_clk = ~out_clk;
end
endmodule

-------------------------

testbench :

module FreqDiv_tb();

wire out_clk;
reg in_clk;
reg rst;

initial
begin
rst = 0;
in_clk = 0;
forever #10 in_clk = ~in_clk;
end

initial
begin
#1000;
rst = 1;
#1000;
rst = 0;
#1000;

#10000 $finish;
end

FreqDivider freqdiv_inst (in_clk, out_clk, _rst);
endmodule


------------------------------

It's an asynchronous design.
Would the RTL (not the testbench) be synthesizable? What about the race
conditions?

Thanks very much in advance.

 

[Neo]

Its synchronous design since you are synchronising to a clock input and
there are no race conditions in your code.

 

[Neo]

well, I overlooked, change the out_clk = ~out_clk; to
out_clk <= ~out_clk;

 

[Berty]

You mention having two clock 60M and 30M, as well as that the second is
divide of the first however what does divide mean as divide can be done
using single FF it can also be done with PLL and so on and each have
its own pro/con and effect. And base on this you need to consider the
effect of skew , jitter, phase etc, as your test bench should be as
accurate as your real board to get good testing converge and real
testing.
Also is the 30M affected by reset as you did as if not you should
remove the reset from the 30M clock.

As for code "style" here few comments you might want to consider:
..
It is advisable not to have same variable in different module so you
might want to put the initial of rst to 0 in the initial that handle
the rst logic.

Don't mix = and <= , use <= for FF and = anywhere else.

No need to put begin end when there is only one line or one condition
(which can be spread on few line) this is of course personal opinion
but myself I rather look on code that is 50 line long than 100 line due
to all those begin end everywhere.

When instantiating use explicit name and not base on position this is
very dangerous.

To answer you question is the RTL will be synthesizable this depend of
course on how you wrote your RTL.

As for race condition you need first to figure what the relation
between the two clocks source you have and if your design take this
into account there should be no race problem.

Also consider using the 30M as clock enable and not as clock and than
you can run everything in the 60M.

Have fun