Frequency detection

[temo_aldorado]

Hello group
I'm new to verilog, so please bear with me. For couple days now, I’m trying to implement this simple freq detection on MAXII cpld for my diy audio dac, and by now I’m quite frustrated.
Thing is, I have 2 master clocks, one for 44.1khz sampling rate (22.57Mhz) and second for 48khz (24.57Mhz). I need to detect incoming bit clock from I2S interface, and set flag accordingly. Incoming bit clock is synchronous derivative from one of two master clocks (mst1_clk/2 or /4 or /8) or (mst2_clk/2 or /4 or /8) so 6 flags to set total
How could this could be implemented using least amount of LC’s
I have all of those derivative frequencies generated on board, so my idea was just comparing incoming bit clock with them, like setting 16 bit register on every edge of one of mst_clk’s and then comparing output. But till now code is ether non synthesizable or takes too much LC’s. So basically what I need is either a hole new approach (probably) or just a small piece of synthesizable verilog code, that compares 2 frequencies and outputs flag if they match

Thanks for reading

 

[rickman]

On Apr 26, 2:57 pm, temo_aldorado <u...@compgroups.net/> wrote:

Hello group,
I'm new to verilog, so please bear with me. For couple days now, I’m trying to implement this simple freq detection on MAXII cpld for my diy audio dac, and by now I’m quite frustrated.
Thing is, I have 2 master clocks, one for 44.1khz sampling rate (22.57Mhz) and second for 48khz (24.57Mhz). I need to detect incoming bit clock from I2S interface, and set flag accordingly. Incoming bit clock is synchronous derivative from one of two master clocks (mst1_clk/2 or /4 or /8) or (mst2_clk/2 or /4 or /8) so 6 flags to set total.
How could this could be implemented using least amount of LC’s ?
I have all of those derivative frequencies generated on board, so my idea was just comparing incoming bit clock with them, like setting 16 bit register on every edge of one of mst_clk’s and then comparing output. But till now code is ether non synthesizable or  takes too much LC’s. So basically what I need is either a hole new approach (probably) or  just a small piece of synthesizable verilog code, that compares 2 frequencies and outputs flag if they match.

Thanks for reading.

You have multiple clocks and an incoming I2S bit clock. Are you
saying you want to figure out which master clock the bit clock is
synchronous to? That shouldn't be too hard.

Use two FFs to detect the edge of the incoming clock relative to both
two phases of your reference clocks and see which detectors never
change the value they see. This will require six FFs and very few
LUTs for each reference clock. You have to sample the reference clock
at two phases because you don't know the phase of the sampled clock vs
the reference clock and either phase may be sampling it while it is
changing.

So for each phase of each reference you will use two FFs to serially
sample the incoming bit clock, then a FF to detect when the two are
different. If you find the two sampling FFs are never different, your
reference clock is synchronous with the bit clock and has a phase that
allows it to be sampled cleanly. You don't want to use two edges of
the reference clock, that will just put the sampling on a bit clock
edge for both detectors at the same time. You need to generate a
timing control that samples at two points 90 degrees out of phase. So
for the mst_clk/2 reference, use both mst_clk and mst_clk~ as your
clock for two circuits, but use an enable so they sample at mst_clk/
2. The slower rates can just use mst_clk for a clock and the enable
can control sampling so it is 90 degrees out of phase. You will need
a reset control to start these circuits and then check the result
after some number of clocks.

Does that make sense?

Thinking out loud of another approach would be to use a digital PLL to
set an NCO to the incoming bit clock. The value of the NCO setting
ultimately found will tell you the frequency of the bit clock. If you
only need to test six possible frequencies the above "per reference"
detectors will likely be smaller. But the DPLL/NCO will let you
search for any rate. Actually, if a freq measurement is appropriate,
a freq counter design is pretty simple and pretty accurate and will be
easier to design than a DPLL/NCO.

Rick