E
Espen Tallaksen
Guest
The webinars are hosted by Aldec as follows: Thursday 26 April:
EU: 3:00 PM â 4:00 PM (CEST) : https://www.aldec.com/en/events/1012
US: 11:00 AM â 12:00 PM (PDT): https://www.aldec.com/en/events/1011
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For an FPGA design we all know that the architecture â all the way from the top to the micro architecture â is critical for both the FPGA quality and the development time. It should be obvious to any experienced designer that this also applies to the testbench.
Most FPGA designs are split into stand-alone modules â for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities, and they are normally accessed from a CPU via a standardized register interface, which acts as an abstraction layer. This abstraction allows a safe and efficient control of the complete FPGA.
Such an approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse.
There is however nothing even close to a standard on how to build the testbench architecture, how to access the verification components, how to control them, or how to extend them for more complex functionality.
UVVM provides a very simple and powerful solution for all of this - and has in fact standardized the testbench architecture, the microarchitecture of the verification components and their command/status interface, a set of common commands, debugging support, etc.
This makes it possible for the whole VHDL community to make verification components that have the same architecture, can be integrated the same way, debugged the same way and controlled the same way. Thus, verification components may be shared easily within the VHDL community, allowing designers to build their own test harness much faster than ever before â using a mix of their own and 3rd party VHDL verification components.
Agenda:
- Where is time spent and wasted
- Basic testbenches using a good infrastructure
- Mirroring the design architecture
- Testbench, test harness, verification components
- Test cases and sequencers, transactions and synchronization
- Randomization and Functional Coverage
- The ESA extensions
- Live demo
- Conclusion
- Q&A
This webinar will show how UVVM is standardising the VHDL testbench architecture and also present some of the most important UVVM extensions sponsored by ESA (the European Space Agency)
EU: 3:00 PM â 4:00 PM (CEST) : https://www.aldec.com/en/events/1012
US: 11:00 AM â 12:00 PM (PDT): https://www.aldec.com/en/events/1011
-----------
For an FPGA design we all know that the architecture â all the way from the top to the micro architecture â is critical for both the FPGA quality and the development time. It should be obvious to any experienced designer that this also applies to the testbench.
Most FPGA designs are split into stand-alone modules â for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities, and they are normally accessed from a CPU via a standardized register interface, which acts as an abstraction layer. This abstraction allows a safe and efficient control of the complete FPGA.
Such an approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse.
There is however nothing even close to a standard on how to build the testbench architecture, how to access the verification components, how to control them, or how to extend them for more complex functionality.
UVVM provides a very simple and powerful solution for all of this - and has in fact standardized the testbench architecture, the microarchitecture of the verification components and their command/status interface, a set of common commands, debugging support, etc.
This makes it possible for the whole VHDL community to make verification components that have the same architecture, can be integrated the same way, debugged the same way and controlled the same way. Thus, verification components may be shared easily within the VHDL community, allowing designers to build their own test harness much faster than ever before â using a mix of their own and 3rd party VHDL verification components.
Agenda:
- Where is time spent and wasted
- Basic testbenches using a good infrastructure
- Mirroring the design architecture
- Testbench, test harness, verification components
- Test cases and sequencers, transactions and synchronization
- Randomization and Functional Coverage
- The ESA extensions
- Live demo
- Conclusion
- Q&A
This webinar will show how UVVM is standardising the VHDL testbench architecture and also present some of the most important UVVM extensions sponsored by ESA (the European Space Agency)