Guest
If you are making VHDL testbenches you should be writing proper log messages. You should also make your result-checkers properly report mismatches and also allow positive acknowledge. Equally important - your testbench should time out with a good message when waiting too long for an event to happen. And wouldn't it be nice to report a summary of all notes, warnings, errors, etc. at the end of your simulation, or perhaps stop on the fifth error?
All this is supported in a free and open source (and well documented) VHDL testbench Library from Bitvis.
http://www.bitvis.no/products/bitvis-utility-library
It is my personal opinion that ANYONE making VHDL testbenches should use this kind of library. It really makes you far more efficient, and it helps everybody understand both your testbench and the transcript/log from your simulations.
It is extremely easy to use, and you can watch a free webinar or download a powerpoint file for a brief presentation on this library. A quick-reference and an example testbench for a simple interrupt controller is also provided.
You may load it all down from our website. No registration required.
www.bitvis.no
All this is supported in a free and open source (and well documented) VHDL testbench Library from Bitvis.
http://www.bitvis.no/products/bitvis-utility-library
It is my personal opinion that ANYONE making VHDL testbenches should use this kind of library. It really makes you far more efficient, and it helps everybody understand both your testbench and the transcript/log from your simulations.
It is extremely easy to use, and you can watch a free webinar or download a powerpoint file for a brief presentation on this library. A quick-reference and an example testbench for a simple interrupt controller is also provided.
You may load it all down from our website. No registration required.
www.bitvis.no