T
tom
Guest
I started building a VHDL analysis tool tentatively called VhdlArch.
http://www.confluent.org/wiki/doku.php?id=vhdlarch
Currently VhdlArch only checks syntax, but soon type-checking and
elaboration will be enabled.
Any bug reports are appreciated!
-Tom
http://www.confluent.org/wiki/doku.php?id=vhdlarch
Currently VhdlArch only checks syntax, but soon type-checking and
elaboration will be enabled.
Any bug reports are appreciated!
-Tom