Free Verilog Simulators?

J

Jeff Mucha

Guest
Are there any free verilog simulators that you can do actual work with?

I use NC-Verilog at work on Windows and Unix. I just have a windows machine
at home. Can I write test benches generate timing diagrams at home for home
projects?

-Jeff
 
Sure. Icarus Verilog and GPL-CVER. Both work like a charm and have
partial Verilog-2001 support.

http://www.pragmatic-c.com/gpl-cver/
http://www.icarus.com/eda/verilog/

I maintain pre-compiled Icarus Verilog packages for Windows at
http://armoid.com/icarus.

Cheers

--
PabloBleyerKocik /"I believed that people would become programmers
pbleyer / and not need companies as much. You can see how
@embedded.cl / laughable that was." -- Steve Wozniak
 
Jeff Mucha wrote:

Are there any free verilog simulators that you can do actual work with?

I use NC-Verilog at work on Windows and Unix. I just have a windows machine
at home. Can I write test benches generate timing diagrams at home for home
projects?
Click to expand...
How about the ones Altera and Xilinx supply in their web
downloadable design software?

-- glen
 
Pablo Bleyer Kocik wrote:
Sure. Icarus Verilog and GPL-CVER. Both work like a charm and have
partial Verilog-2001 support.

http://www.pragmatic-c.com/gpl-cver/
http://www.icarus.com/eda/verilog/

I maintain pre-compiled Icarus Verilog packages for Windows at
http://armoid.com/icarus.

Cheers

--
PabloBleyerKocik /"I believed that people would become programmers
pbleyer / and not need companies as much. You can see how
@embedded.cl / laughable that was." -- Steve Wozniak

cver is a much better choice. Not only it supports most of verilog 2001,
Click to expand...
it beats iverilog in simulation performance. cver is much more like a
commercial software in terms of performance (sometimes even faster than
ncverilog in my experience).
 
Jason Zheng wrote:
cver is a much better choice. Not only it supports most of verilog
2001,
it beats iverilog in simulation performance. cver is much more like a

commercial software in terms of performance (sometimes even faster
than
ncverilog in my experience).
Click to expand...
Well, they both have strengths and weaknesses. Icarus generates
intermediate processor files and Cver is monolithic, perhaps that is
why Cver is faster. I have had some problems with the VCD dumps of Cver
being rejected by other tools while the Icarus ones were fine (but
perhaps that is not really a Cver problem).

Cheers.

--
PabloBleyerKocik /"I am overwhelmed by an irresistible temptation
pbleyer / to do my climb by moonlight and unroped."
@embedded.cl / -- William Shockley
 
Icarus is slow because the intermediate representation is taken down to
the bit level.

However, Steve is actively changing the code base to model vector
operations in the IR. This may realize a 10X performance improvement.

Also, I prefer Icarus over Cver due to the organization of the source
code. Even a casual C programmer can get in there to make
improvements, as I did with the FNF code generator.
http://www.confluent.org/wiki/doku.php?id=fnf:main

-Tom
 
What about for viewing timing, how do you generate a dumb file with cver or
iverilog? Do you need a PLI? Can you do it for free? What do you recommend?

Thanks,

Jeff



"Jeff Mucha" <mucha@NoSpamskylab.org> wrote in message
news:wbadnTXgbPrJ32rcRVn-tQ@comcast.com...
Are there any free verilog simulators that you can do actual work with?

I use NC-Verilog at work on Windows and Unix. I just have a windows
machine
at home. Can I write test benches generate timing diagrams at home for
home
projects?

-Jeff
Click to expand...
 
Ok,

Since I'm using windows, I'm going to try GTKwave and Iverilog. Does anyone
have a very simple test bench that calls out the $dumpvars and $dumpfile for
iverilog? Do I need anything else to generate a .vcd file? Is that built
into iverilog?

-Jeff




"Jeff Mucha" <mucha@NoSpamskylab.org> wrote in message
news:wbadnTXgbPrJ32rcRVn-tQ@comcast.com...
Are there any free verilog simulators that you can do actual work with?

I use NC-Verilog at work on Windows and Unix. I just have a windows
machine
at home. Can I write test benches generate timing diagrams at home for
home
projects?

-Jeff
Click to expand...
 
Jeff Mucha wrote:
What about for viewing timing, how do you generate a dumb file with
cver or
iverilog?
Click to expand...
As usual, you select the dump file name with $dumpfile and the
variables to be dumped with $dumpvars. Eg:

initial begin
$dumpfile("mydump.vcd");
$dumpvars(level, mydut1);
$dumpvars(level, mydut2);
end

Really, it ain't rocket science.

Do you need a PLI? Can you do it for free? What do you recommend?
Click to expand...
Cver and Icarus have PLI interfaces if you need more control. Read
their respective documentation. I would strongly suggest using
something like Tom Scheffler's Oroboro to be more productive
(http://apvm.sourceforge.net).

Cheers.

-- /"In seed time learn, in harvest teach, in winter
PabloBleyerKocik/ enjoy. Drive your cart and your plow over the
pbleyer / bones of the dead. The road of excess leads to
@embedded.cl/ the palace of wisdom."- Proverbs of Hell, W. Blake
 
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