N
ngsayjoe@gmail.com
Guest
Hi All Verilogers,
I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.
The current release is only available on WindowsXP platform, however I
plan to port it to Linux once the release is stable. Besides, I'm
working on some basic SystemVerilog support, since it's the superset of
SystemVerilog, hence a full support wouldn't be that difficult. Of
course that is the long term goal as, the SystemVerilog standard
1800-2005 is a huge standard, it will take some time to reach there.
Thanks.
Thanks,
Joe
I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.
The current release is only available on WindowsXP platform, however I
plan to port it to Linux once the release is stable. Besides, I'm
working on some basic SystemVerilog support, since it's the superset of
SystemVerilog, hence a full support wouldn't be that difficult. Of
course that is the long term goal as, the SystemVerilog standard
1800-2005 is a huge standard, it will take some time to reach there.
Thanks.
Thanks,
Joe