Free Verilog Simulator

[ngsayjoe@gmail.com]

Hi All Verilogers,

I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.

The current release is only available on WindowsXP platform, however I
plan to port it to Linux once the release is stable. Besides, I'm
working on some basic SystemVerilog support, since it's the superset of
SystemVerilog, hence a full support wouldn't be that difficult. Of
course that is the long term goal as, the SystemVerilog standard
1800-2005 is a huge standard, it will take some time to reach there.
Thanks.

Thanks,
Joe

 

[Uwe Bonnes]

ngsayjoe@gmail.com <ngsayjoe@gmail.com> wrote:

Hi All Verilogers,

I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.

The current release is only available on WindowsXP platform, however I
plan to port it to Linux once the release is stable. Besides, I'm
working on some basic SystemVerilog support, since it's the superset of
SystemVerilog, hence a full support wouldn't be that difficult. Of
course that is the long term goal as, the SystemVerilog standard
1800-2005 is a huge standard, it will take some time to reach there.
Thanks.

Why so many different efforts for a free verilog compiler?

There already are Cver and Icarus Verilog to my knowledge . Improving the
existing code base seems more usefull to me than creating a new code base
....

But don't mind my humble opinion...
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 

[Allan Herriman]

On Wed, 1 Feb 2006 15:38:24 +0000 (UTC), Uwe Bonnes
<bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

ngsayjoe@gmail.com <ngsayjoe@gmail.com> wrote:
Hi All Verilogers,

I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.

The current release is only available on WindowsXP platform, however I
plan to port it to Linux once the release is stable. Besides, I'm
working on some basic SystemVerilog support, since it's the superset of
SystemVerilog, hence a full support wouldn't be that difficult. Of
course that is the long term goal as, the SystemVerilog standard
1800-2005 is a huge standard, it will take some time to reach there.
Thanks.

Why so many different efforts for a free verilog compiler?

There already are Cver and Icarus Verilog to my knowledge . Improving the
existing code base seems more usefull to me than creating a new code base

The OP isn't interested in open source; he wants to make a commercial
product.
Making the early versions freeware is a good way of exposing the
nascent tool to a number of different Verilog designs in the wild.
He's hoping for bug reports and user feedback.

Regards,
Allan

 

[Stephen Williams]

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Hash: SHA1

Allan Herriman wrote:

On Wed, 1 Feb 2006 15:38:24 +0000 (UTC), Uwe Bonnes
bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

ngsayjoe@gmail.com <ngsayjoe@gmail.com> wrote:
Hi All Verilogers,
I recently developed a new Verilog Simulator and it's free for the time
being.


There already are Cver and Icarus Verilog to my knowledge . Improving the
existing code base seems more usefull to me than creating a new code base

The OP isn't interested in open source; he wants to make a commercial
product.
Making the early versions freeware is a good way of exposing the
nascent tool to a number of different Verilog designs in the wild.
He's hoping for bug reports and user feedback.

It's even more blatant then that. The web page says that it is
a "free trial". By that evidence, the original post smells to me
like a commercial advertisement, a bait-and-switch. A $500 price
tag for the released version, according to the FAQ. (In fairness,
they seem to be saying they do not have a "stable" sellable
version yet.)

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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[ngsayjoe@gmail.com]

The reason I came out with another Verilog Simulator is because,
there's no cheap and good and user-friendly ones. The free ones are
buggy and hard to use (Icarus, etc.). Whereas the stable and
user-friendly ones are very expensive (ModelSim, Aldec, etc.). I'm here
to solve the problems of price and functionality, $500 is affordable to
most people.

Stephen Williams wrote:

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Allan Herriman wrote:
On Wed, 1 Feb 2006 15:38:24 +0000 (UTC), Uwe Bonnes
bon@hertz.ikp.physik.tu-darmstadt.de> wrote:

ngsayjoe@gmail.com <ngsayjoe@gmail.com> wrote:
Hi All Verilogers,
I recently developed a new Verilog Simulator and it's free for the time
being.


There already are Cver and Icarus Verilog to my knowledge . Improving the
existing code base seems more usefull to me than creating a new code base

The OP isn't interested in open source; he wants to make a commercial
product.
Making the early versions freeware is a good way of exposing the
nascent tool to a number of different Verilog designs in the wild.
He's hoping for bug reports and user feedback.

It's even more blatant then that. The web page says that it is
a "free trial". By that evidence, the original post smells to me
like a commercial advertisement, a bait-and-switch. A $500 price
tag for the released version, according to the FAQ. (In fairness,
they seem to be saying they do not have a "stable" sellable
version yet.)

- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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Version: GnuPG v1.2.5 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org

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KUdZEUkprGWTYD4XNgtSr2M=
=3KsK
-----END PGP SIGNATURE-----

 

[Frank]

<ngsayjoe@gmail.com> wrote in message
news:1138786562.578659.52930@z14g2000cwz.googlegroups.com...

Hi All Verilogers,

I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.

Oh, there are many open source simulators out there, improvement on the
interface will make it interesting than a new kernel.

 

[ngsayjoe@gmail.com]

The implemtation of existing open-source Verilog Simulator kernels are
not efficient and optimal, and most of them are under-developed. No
offense here, but sometimes it's better to rebuilt than to improve on
some badly design software. Besides, what about mixed-language support?
What is their plans of SystemVerilog support? SystemVerilog support is
on the top of LogicSim roadmap, and the kernel is design with this in
mind. And afterall, the development of the entire parser and kernel are
already complete. Now I'm spending most of my time on improving the
graphical user-interface and debugging tools.

Finally, the main reason I do not make it open-source is because, we
need some money in order to further improve on our R&D, and also make
some living. Thanks.

Frank wrote:

ngsayjoe@gmail.com> wrote in message
news:1138786562.578659.52930@z14g2000cwz.googlegroups.com...
Hi All Verilogers,

I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.


Oh, there are many open source simulators out there, improvement on the
interface will make it interesting than a new kernel.

 

[Paul Johnson]

On 2 Feb 2006 00:16:00 -0800, "ngsayjoe@gmail.com"
<ngsayjoe@gmail.com> wrote:

The reason I came out with another Verilog Simulator is because,
there's no cheap and good and user-friendly ones. The free ones are
buggy and hard to use (Icarus, etc.).

Oh dear. I think it's pretty good.

A bit of free advice: if you want people to find the bugs in your
'recently developed' simulator, rather than Steve's 10(?)-year-old
one, then you're going to have to incentivise them. The offer of a
"free" alpha test is not likely to go down well with most people.

 

[Jason Zheng]

ngsayjoe@gmail.com wrote:

The reason I came out with another Verilog Simulator is because,
there's no cheap and good and user-friendly ones. The free ones are
buggy and hard to use (Icarus, etc.). Whereas the stable and
user-friendly ones are very expensive (ModelSim, Aldec, etc.). I'm here
to solve the problems of price and functionality, $500 is affordable to
most people.
I understand that you want to make a commercial verilog simulator with

free alpha testers, but there are several reasons why people won't
alpha-test it for you:

1. It doesn't offer anything better than the currently available free
simulators like icarus and cver. Sure it supports some systemverilog,
but like you said, it's only the basic functions.

2. It's windows only. If you want to make a successful verilog
simulator, it HAS to run on multiple platforms. A lot of people prefer
non-windows workstations. There's nothing about a verilog simulator that
has to depend on a windows operating system. Making it portable is much
very worth the effort.

3. The reason why a lot people volunteer to alpha and beta-test
softwares for FREE is usually because the software is FREE, and will
remain free. You intention is clearly to make profits from this
software, so that discourages people. There's a price to pay for keeping
software proprietary, and that is "no free testing". You can't have it
both ways.


just my 2 cents,

jz

 

[Jason Zheng]

ngsayjoe@gmail.com wrote:

The implemtation of existing open-source Verilog Simulator kernels are
not efficient and optimal, and most of them are under-developed. No
offense here, but sometimes it's better to rebuilt than to improve on
some badly design software. Besides, what about mixed-language support?

IMO, there is no "optimal" software, only "better" software. Sure the
current ones may not support the latest language features and slower
than the commercial products, but they are GPL free and are good
solutions for many tasks. I agree that it's better to start from fresh
when you have better ideas about architecture, but you are offending a
lot people already by bashing their software.

What is their plans of SystemVerilog support? SystemVerilog support is
on the top of LogicSim roadmap, and the kernel is design with this in
mind. And afterall, the development of the entire parser and kernel are
already complete. Now I'm spending most of my time on improving the
graphical user-interface and debugging tools.

Complete? I thought your software is still buggy and lack most of the

SystemVerilog features? And I strongly suggest that you go with some
cross-platform graphical widget to ensure future portability.

Finally, the main reason I do not make it open-source is because, we
need some money in order to further improve on our R&D, and also make
some living. Thanks.

Like I posted earlier, if you want free testers, you have to give them
something free in return. Maybe you can keep an open source version and
a commercial version like Pragmatic-C is currently doing? By keeping it
open-source, you will also get free developers contributing their time
to find bugs for you .

 

[Allan Herriman]

On Thu, 02 Feb 2006 09:49:26 +0000, Paul Johnson <abuse@127.0.0.1>
wrote:

On 2 Feb 2006 00:16:00 -0800, "ngsayjoe@gmail.com"
ngsayjoe@gmail.com> wrote:

The reason I came out with another Verilog Simulator is because,
there's no cheap and good and user-friendly ones. The free ones are
buggy and hard to use (Icarus, etc.).

Oh dear. I think it's pretty good.

A bit of free advice: if you want people to find the bugs in your
'recently developed' simulator, rather than Steve's 10(?)-year-old
one, then you're going to have to incentivise them. The offer of a
"free" alpha test is not likely to go down well with most people.

Haneef Mohammad wrote a VHDL simulator in the late '90s. He developed
it along similar lines. His 'free' stage lasted a couple of years
though.
I think I submitted dozens of bug reports and enhancement requests in
that time, in the hope that Haneef would be able to make a better
product.
In my case, I knew the end result wouldn't be open source, but I still
felt it was worthwhile, as (at the time) there was no good VHDL
simulator in the $300 price range.

Here it is:
http://www.symphonyeda.com/default.htm

Allan

 

[Terry Brown]

Well, at this point, it seems not particularly usable since it fails on
this simple line of verilog code

$display("p=%x s=%x d=%x", p, s, d);

where p, s, and d are reg[31:0];

with the message:

INTERNAL ERROR: Unsupported format in
lsim_sys_task_display::get_string_i_format

Also, it wants a single file to simulate, prompts each time for the top
module, and doesn't allow copying text from the result window . . .

Enough. I won't spend any more time on it.

Terry


On Wed, 01 Feb 2006 01:36:02 -0800, ngsayjoe@gmail.com wrote:

Hi All Verilogers,

I recently developed a new Verilog Simulator and it's free for the time
being. I'd like to get some users to use it and hope for some valuable
feedbacks. The current release (v1.4) is still not very stable yet,
however it can support most of the basic Verilog constucts. But some
advanced features such as "generate" is yet to be supported. It's
available for download at http://www.logicsim.com and it's currently
named LogicSim.

The current release is only available on WindowsXP platform, however I
plan to port it to Linux once the release is stable. Besides, I'm
working on some basic SystemVerilog support, since it's the superset of
SystemVerilog, hence a full support wouldn't be that difficult. Of
course that is the long term goal as, the SystemVerilog standard
1800-2005 is a huge standard, it will take some time to reach there.
Thanks.

Thanks,
Joe

 

[Stephen Williams]

ngsayjoe@gmail.com wrote:

No
offense here, but sometimes it's better to rebuilt than to improve on
some badly design software.

Hey! No fair claiming "better design" when no one (but you) can
see your design and judge for themselves.

And for the record, I have no complaints with you wanting to sell
a Verilog simulator, but a) you presented your alpha test of a
commercial product as "free", which it isn't, and b) advertisement
of commercial products is frowned upon in this forum.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Stephen Williams]

ngsayjoe@gmail.com wrote:

Finally, the main reason I do not make it open-source is because, we
need some money in order to further improve on our R&D, and also make
some living. Thanks.

If I had only accepted 1/2 the contract support requests I'd
received over the years...

Alas.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Stephen Williams]

Terry Brown wrote:

Well, at this point, it seems not particularly usable since it fails on
this simple line of verilog code

$display("p=%x s=%x d=%x", p, s, d);

where p, s, and d are reg[31:0];

with the message:

INTERNAL ERROR: Unsupported format in
lsim_sys_task_display::get_string_i_format

Actually, strictly speaking, %x is not a valid Verilog display format
string according to the Verilog-2001 LRM. I think you meant %h? In
practice, it's common for tools to accept %x as a synonym for %h.



--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[General Schvantzkoph]

On Thu, 02 Feb 2006 00:16:00 -0800, ngsayjoe@gmail.com wrote:

The reason I came out with another Verilog Simulator is because, there's
no cheap and good and user-friendly ones. The free ones are buggy and
hard to use (Icarus, etc.). Whereas the stable and user-friendly ones
are very expensive (ModelSim, Aldec, etc.). I'm here to solve the
problems of price and functionality, $500 is affordable to most people.

Good luck to you but you should be aware that no one has ever succeeded
with your business model. In order to make any money with a $500 product
your support cost has to be very nearly 0 and that's unlikely with a new
Verilog simulator. Then you have to be able to sell a large number of
licenses, at least 500 per employee, just to cover your costs. That's
going to be very difficult given that there is already a popular free
Verilog simulator. In addition to Icarus, Xilinx is also offering their
own simulator in their tools. Currently the Xilinx simulator is useless
but you have to figure that by the time you've gotten your simulator to
the point where someone could trust a project to it the Xilinx simulator
will also have reached the point of being useful. Xilinx has vast
resources and their business model treats tools as a means of selling
FPGAs not as a profit center in themselves so they can afford to spend
more money on their simulator then you can on yours and they can give it
away just like they give away their synthesis tools.

 

[ngsayjoe@gmail.com]

when you have better ideas about architecture, but you are offending a
lot people already by bashing their software.

I am really sorry, I didn't mean to bash.

I understand that you want to make a commercial verilog simulator with
free alpha testers

I think i may not have made my intentions clear in my earlier post,
please disregard it as i can see now it can be quite
offensive when looked at from different perspectives. I will try now
again to describe the purpose of this initial free version.

Here's what i do not expect or want/but will not reject
1)Free testing without incentives
2)Bug fixes
3)Financial support before a stable release

But here's what i would be really grateful for
1)Expectations from future users on what they would like to see
added/currently missing
2)Pricing expectations
3)What do you really want to see in version 1.5?

commercial product as "free", which it isn't, and b) advertisement
of commercial products is frowned upon in this forum.

However, this is not an advertisement, it's more like a press-release.

INTERNAL ERROR: Unsupported format in
lsim_sys_task_display::get_string_i_format

It looks like an underdevelopped piece of software. Otherwise it would be
able to find out the syntax errors instead of crash.

This is actually a properly handled exception, it's not a crash.
However, i agree that i need to properly report the syntax error back
to the user.

 

[Terry Brown]

Oops, I have embarassed myself--writing too much c code . . .

In fact, LogicSim fails on the following:

$display("p=%d s=%d d=%d", p, s, d);

with the same error.

And this format does work--at least in Modelsim and cver.

When I saw that failure originally, I thought--hmm, what if I change to
hex format, but I was in c mode.

Sorry for the confusion--but my point stands.

On Thu, 02 Feb 2006 11:38:45
-0800, Stephen Williams wrote:

Terry Brown wrote:
Well, at this point, it seems not particularly usable since it fails on
this simple line of verilog code

$display("p=%x s=%x d=%x", p, s, d);

where p, s, and d are reg[31:0];

with the message:

INTERNAL ERROR: Unsupported format in
lsim_sys_task_display::get_string_i_format

Actually, strictly speaking, %x is not a valid Verilog display format
string according to the Verilog-2001 LRM. I think you meant %h? In
practice, it's common for tools to accept %x as a synonym for %h.

 

[Chris F Clark]

While this doesn't have much (if anything) to do with Verilog....

I challenge some of the numbers that General Schvantzkoph
<schvantzkoph@yahoo.com> wrote. I don't think it takes 500 users *
$500 per employee to cover costs--that works out to $250000 (I presume
per year). That makes sense if you are doing this as sole source of
income, have leased office space, want a roughly 6-figure salary, and
have more that 50% overhead. If you are doing this as a 2nd job, want
only supllementary income, do it out of your "garage", and so forth,
then you can get by on surprisingly small revenue stream. It simply
needs to exceed your "hassle-factor".

The real question is why you are writing and selling the tool. If you
want to get rich, then you are likely to be disappointed. If you have
a desire to create something and the commitment to make it worthwhile,
you'll probably succeed. Along the way, you'll probably get to know
some very interesting people, your users. And, you can make "some"
money. In other words, don't quit your day job.

BTW, I know of no specific proscription against commercial
announcements in this newsgroup (maybe I just haven't read the ng's
faq recently enough). However, from experience I can tell you that
newsgroups generate very little direct commercial interest. The
people who read and post in newsgroups are generally not the ones
making "buy" decisions, although they can be lead architects who have
some clout. Therefor, even if it isn't prohibited, it isn't your best
marketing strategy--although it can help if you can use answering
questions on the ng to position yourself as an expert. It might be
different (more effective) if your product had a $50-100 price tag and
was sutiable for student/hobbyist use. Especially, if it came comlete
with the answers to "homework questions" ;-)!!!

Hope this helps,
-Chris

*****************************************************************************
Chris Clark Internet : compres@world.std.com
Compiler Resources, Inc. Web Site : http://world.std.com/~compres
23 Bailey Rd voice : (508) 435-5016
Berlin, MA 01503 USA fax : (978) 838-0263 (24 hours)
------------------------------------------------------------------------------

 

[Frank]

"Terry Brown" <tthkbw@gmail.com> wrote in message
newsan.2006.02.02.19.04.43.328125@gmail.com...

Well, at this point, it seems not particularly usable since it fails on
this simple line of verilog code

$display("p=%x s=%x d=%x", p, s, d);

where p, s, and d are reg[31:0];

with the message:

INTERNAL ERROR: Unsupported format in
lsim_sys_task_display::get_string_i_format

Also, it wants a single file to simulate, prompts each time for the top
module, and doesn't allow copying text from the result window . . .

Enough. I won't spend any more time on it.

Terry

It looks like an underdevelopped piece of software. Otherwise it would be
able to find out the
syntax errors instead of crash.