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cvc.training@gmail.com
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Quest for Scalable Verification => result:
Questa + OVM
With ever growing complexities of ASICs (and FPGAs), the task of
verifying them has become a never-say-done activity. Given the need
for multiple levels of reuse in design and verification, a stand-still
approach to verification doesnt hold good any longer. It requires
continuous inflow of new ideas, thoughts and technologies to address
the complex requirements. Hence the quest for a scalable verification
has been a continuous one. A series of innovative, path breaking
technologies have emerged over the last decade to address the
verification challenges. Back in 2005 IEEE standardized SystemVerilog
as the standard HDVL to incorporate many of these technologies with a
Verilog flavor. Since then SV has been making its way into being the
most preferred language for ASIC Design and Verification across the
globe. However leading edge semiconductor houses have quickly realized
that using SystemVerilog on its own might lead to sub-optimal benefits
especially in Verification. This is due to the fact that the language
is vast and not every team has enough time to experiment with the
right usage model for the task at hand. This is the primary motivation
behind adopting a Verification Methodology - to get more productive in
less time.
OVM as announced in late 2007/early 2008 is proving to be a very good
choice for building such scalable verification infrastructure as it
has all the classical methodology features plus some of the most
advanced, proven verification techniques such as Virtual sequences,
factories etc. The good thing about OVM is it is open, and there is a
vibrant ecosystem building around OVM. We at CVC have an everlasting
thirst to be on top of any new verification technology. As part of
Mentors Questa Vanguard program, CVC has had the privilege of
experiencing the power of OVM early with a robust, easy-to-use
verification platform Questa!
As with any new technology, the initial adoption requires some ramp up
time. During our early engagements with building OVM compliant
verification environments we went through a series of learning steps.
As a result of it, we at CVC recently composed a step-by-step OVM
quick start guide that we share with our customers. In this seminar,
we share an early preview of this step-by-step guide with a simple
packet de-serializer design. We walk through the following topics:
SystemVerilog features for Verification
OVM introduction
DUV - Packet de-serializer
Step-by-step OVM approach with code snippets
Highlights of important Questa features that helped us in the process
Results, summary and looking forward
To attend this seminar: Click on: Register for CVC OVM with Questa
seminar.
If the above link doesnt work, send an email to
mailto:cvc.training@gmail.com;
?subject=CVC_OVM_Questa Please include the following details in your
email.
Name:
Company Name:
Official Email ID:
Contact Number:
Venue: CVC Bangalore Office (Ground Floor)
Date: 2nd Aug 2008, Saturday at 15.00 (3.00 PM)
Agenda: 1 hour presentation followed by a quick demo + Q&A
Questa + OVM
With ever growing complexities of ASICs (and FPGAs), the task of
verifying them has become a never-say-done activity. Given the need
for multiple levels of reuse in design and verification, a stand-still
approach to verification doesnt hold good any longer. It requires
continuous inflow of new ideas, thoughts and technologies to address
the complex requirements. Hence the quest for a scalable verification
has been a continuous one. A series of innovative, path breaking
technologies have emerged over the last decade to address the
verification challenges. Back in 2005 IEEE standardized SystemVerilog
as the standard HDVL to incorporate many of these technologies with a
Verilog flavor. Since then SV has been making its way into being the
most preferred language for ASIC Design and Verification across the
globe. However leading edge semiconductor houses have quickly realized
that using SystemVerilog on its own might lead to sub-optimal benefits
especially in Verification. This is due to the fact that the language
is vast and not every team has enough time to experiment with the
right usage model for the task at hand. This is the primary motivation
behind adopting a Verification Methodology - to get more productive in
less time.
OVM as announced in late 2007/early 2008 is proving to be a very good
choice for building such scalable verification infrastructure as it
has all the classical methodology features plus some of the most
advanced, proven verification techniques such as Virtual sequences,
factories etc. The good thing about OVM is it is open, and there is a
vibrant ecosystem building around OVM. We at CVC have an everlasting
thirst to be on top of any new verification technology. As part of
Mentors Questa Vanguard program, CVC has had the privilege of
experiencing the power of OVM early with a robust, easy-to-use
verification platform Questa!
As with any new technology, the initial adoption requires some ramp up
time. During our early engagements with building OVM compliant
verification environments we went through a series of learning steps.
As a result of it, we at CVC recently composed a step-by-step OVM
quick start guide that we share with our customers. In this seminar,
we share an early preview of this step-by-step guide with a simple
packet de-serializer design. We walk through the following topics:
SystemVerilog features for Verification
OVM introduction
DUV - Packet de-serializer
Step-by-step OVM approach with code snippets
Highlights of important Questa features that helped us in the process
Results, summary and looking forward
To attend this seminar: Click on: Register for CVC OVM with Questa
seminar.
If the above link doesnt work, send an email to
mailto:cvc.training@gmail.com;
?subject=CVC_OVM_Questa Please include the following details in your
email.
Name:
Company Name:
Official Email ID:
Contact Number:
Venue: CVC Bangalore Office (Ground Floor)
Date: 2nd Aug 2008, Saturday at 15.00 (3.00 PM)
Agenda: 1 hour presentation followed by a quick demo + Q&A