Free GUI top level integration tool for Verilog and VHDL

VTC has been developed for very long time. It has been used in many
projects and proven to be useful. It should have been available for
you long time ago. But I have to spend many years to study laws alone
to face to the lawyers from leading EDA, because the counsel fee is
too expensive for me. Not long ago, finally my patent was judged to be
valid. So I have time to build this website to show some of my ideas.
http://www.veriloghdl.org
Thanks.

 

Hi,
Pleased to introduce my new tool, VTM 2012. It is intended to be a
table based edit tool for Verilog/VHDL module's interface definition,
and unify the process of HDL coding and document writing. A demo is at
http://www.veriloghdl.org/demo.html
These tools enable you to build the design's framework, both top down
and bottom up styles. I want to design the HDL in even higher level. I
would like to get some ideas on how people think it before VTM's
completeness. I am now considering to add system verilog interface
feature to it. But I see very few people using system verilog feature
like interface in their RTL designs. Do you think it a valuable
feature? Any comment is welcome.
Thanks

 

[wzab]

On 12 Mar, 15:57, vtxsupp...@hotmail.com wrote:

Hi,
Pleased to introduce my new tool, VTM 2012. It is intended to be a
table based edit tool for Verilog/VHDL module's interface definition,
and unify the process of HDL coding and document writing. A demo is athttp://www.veriloghdl.org/demo.html
These tools enable you to build the design's framework, both top down
and bottom up styles. I want to design the HDL in even higher level. I
would like to get some ideas on how people think it before VTM's
completeness. I am now considering to add system verilog interface
feature to it. But I see very few people using system verilog feature
like interface in their RTL designs. Do you think it a valuable
feature? Any comment is welcome.
Thanks

How does it compare to the old good and free Perlilog (
http://www.billauer.co.il/perlilog.html )?
--
Regards,
WZab

 

Hi WZab,
I think all the tools for top level integration have the similar object and outputs. The difference is how to use them.
VTC is very different from other tools.
A good and quick way to learn VTC is through a quick demo at http://www.veriloghdl.org/demos/demo1.htm
Users' goal is to instantiate and connect modules. I saw many people dislike such a job. I think through this job one can get a clear knowledge of the whole project and a sense of achievement. VTC is very easy to learn. You can even start to use it without learning. At the same time, many powerful function can guide user's operation.
One aim of VTC is to cost users' least operation. User can directly get the correct result because no opportunity to make a mistake. Users need not to learn additional complicated rules.
I hope this answers your question. For detailed comparisons, you can give a sample and your current way. I will describe how VTC do it.

Thanks