FPGAs and DDR2 memory

[Glen Gibb]

Hi all,

I'm working on a V2P design that interfaces to DDR2 memory. There seems
to be very little information in regards to working DDR2 memory designs
with V2P devices. Has anyone successfully implemented a DDR2 design with
the V2P? (I'm using the Xilinx Memory Interface Generator.)

Also, for those who have successfully implemented DDR2 interfaces on ANY
FPGAs, what general constraints/rules did you following in layout and
routing? (Particularly when using components rather than DIMMS.)

Thanks in advance,
Glen