R
rootz
Guest
I have a design on Virtex II that tests sram controller. To save pins,
the sram is always enabled and in a non-sleep mode. My test app is able
to read and write to the sram. Upon reconfiguration of the fpga, it
stops talking to the sram. It only resumes reading and writing to the
sram only when the entire board is reset (or system rebooted). Anyone
experienced this problem before? Does this have anything to do with the
IO pins possibly glitching during reconfiguration.
Xilinx Answer records also says IO buffers might be in a high state
during reconfiguration. I am not sure how this should affect the sram
communication.
the sram is always enabled and in a non-sleep mode. My test app is able
to read and write to the sram. Upon reconfiguration of the fpga, it
stops talking to the sram. It only resumes reading and writing to the
sram only when the entire board is reset (or system rebooted). Anyone
experienced this problem before? Does this have anything to do with the
IO pins possibly glitching during reconfiguration.
Xilinx Answer records also says IO buffers might be in a high state
during reconfiguration. I am not sure how this should affect the sram
communication.