FPGA serial programming troubles. (Virtex II)

B

Brijesh

Guest
We have a board with 2 Virtex II 6000 devices. They are programmed from
independent bank of serial eeproms in Master serial mode.

One of the FPGA's (slave fpga) is not being programmed consistently. On
power up it sometimes programs and at times fails. If after powerup we
manually start a programming cycle by pulling program pin low, it
programs properly. Observed INIT pin going low before DONE goes high on
slave FPGA, indicating CRC error.

Also observed that slave FPGA initiates the program cycle earlier and
has higher serial clock frequency than master.(using the lowest
frequency 4 MHz)

Hooked up logic analyzer and counted the clock cycles in the programming
cycle. The slave FPGA clock count varies, both when it fails and when
it programs(manual program intiation). When it fails it is lower than
the required count but varies from one try to another. When it succeeds
it is higher than required and also vaires from one try to another.

Master FPGA clock count is always the same.

Any suggestions on what could be causing this problem?

Thanks
Brijesh
 
It seems to me that the Master tries to start programming too early after
power-up.

Peter Alfke
=============
From: Brijesh <brijesh_xyz@cfrsi_xyz.com
Organization: Virginia Tech, Blacksburg, Virginia, USA
Newsgroups: comp.arch.fpga
Date: Mon, 14 Jun 2004 16:50:38 -0400
Subject: FPGA serial programming troubles. (Virtex II)

We have a board with 2 Virtex II 6000 devices. They are programmed from
independent bank of serial eeproms in Master serial mode.

One of the FPGA's (slave fpga) is not being programmed consistently. On
power up it sometimes programs and at times fails. If after powerup we
manually start a programming cycle by pulling program pin low, it
programs properly. Observed INIT pin going low before DONE goes high on
slave FPGA, indicating CRC error.

Also observed that slave FPGA initiates the program cycle earlier and
has higher serial clock frequency than master.(using the lowest
frequency 4 MHz)

Hooked up logic analyzer and counted the clock cycles in the programming
cycle. The slave FPGA clock count varies, both when it fails and when
it programs(manual program intiation). When it fails it is lower than
the required count but varies from one try to another. When it succeeds
it is higher than required and also vaires from one try to another.

Master FPGA clock count is always the same.

Any suggestions on what could be causing this problem?

Thanks
Brijesh
Click to expand...
 
Hello Peter,

Did you mean the slave FPGA? Thats the one that is giving trouble and
starts programming 1ms earlier than master.

What factors can cause this on a FPGA?
Both master and slave share the ground and power planes.
Is the poweron voltage ramp causing the issue? Since they both share
power planes it should affect both the same way. So poweron voltage ramp
is probably not the issue.

Thanks for taking time out to respond.
Brijesh




Peter Alfke wrote:
It seems to me that the Master tries to start programming too early after
power-up.

Peter Alfke
=============

From: Brijesh <brijesh_xyz@cfrsi_xyz.com
Organization: Virginia Tech, Blacksburg, Virginia, USA
Newsgroups: comp.arch.fpga
Date: Mon, 14 Jun 2004 16:50:38 -0400
Subject: FPGA serial programming troubles. (Virtex II)

We have a board with 2 Virtex II 6000 devices. They are programmed from
independent bank of serial eeproms in Master serial mode.

One of the FPGA's (slave fpga) is not being programmed consistently. On
power up it sometimes programs and at times fails. If after powerup we
manually start a programming cycle by pulling program pin low, it
programs properly. Observed INIT pin going low before DONE goes high on
slave FPGA, indicating CRC error.

Also observed that slave FPGA initiates the program cycle earlier and
has higher serial clock frequency than master.(using the lowest
frequency 4 MHz)

Hooked up logic analyzer and counted the clock cycles in the programming
cycle. The slave FPGA clock count varies, both when it fails and when
it programs(manual program intiation). When it fails it is lower than
the required count but varies from one try to another. When it succeeds
it is higher than required and also vaires from one try to another.

Master FPGA clock count is always the same.

Any suggestions on what could be causing this problem?

Thanks
Brijesh
Click to expand...
 
Semantic confusion:
It seems that your board fails in slave mode. In slave mode the FPGA is not
in charge of generating CCLK, it is at the mercy of a foreign master who
generates the clock.
My thought is that this foreign master is too impatient and starts the
clocking too early, before the FPGA is ready.
Just a thought...
Peter Alfke
==========
From: Brijesh <brijesh_xyz@cfrsi_xyz.com
Organization: Virginia Tech, Blacksburg, Virginia, USA
Newsgroups: comp.arch.fpga
Date: Tue, 15 Jun 2004 09:58:36 -0400
Subject: Re: FPGA serial programming troubles. (Virtex II)

Hello Peter,

Did you mean the slave FPGA? Thats the one that is giving trouble and
starts programming 1ms earlier than master.

What factors can cause this on a FPGA?
Both master and slave share the ground and power planes.
Is the poweron voltage ramp causing the issue? Since they both share
power planes it should affect both the same way. So poweron voltage ramp
is probably not the issue.

Thanks for taking time out to respond.
Brijesh




Peter Alfke wrote:
It seems to me that the Master tries to start programming too early after
power-up.

Peter Alfke
=============

From: Brijesh <brijesh_xyz@cfrsi_xyz.com
Organization: Virginia Tech, Blacksburg, Virginia, USA
Newsgroups: comp.arch.fpga
Date: Mon, 14 Jun 2004 16:50:38 -0400
Subject: FPGA serial programming troubles. (Virtex II)

We have a board with 2 Virtex II 6000 devices. They are programmed from
independent bank of serial eeproms in Master serial mode.

One of the FPGA's (slave fpga) is not being programmed consistently. On
power up it sometimes programs and at times fails. If after powerup we
manually start a programming cycle by pulling program pin low, it
programs properly. Observed INIT pin going low before DONE goes high on
slave FPGA, indicating CRC error.

Also observed that slave FPGA initiates the program cycle earlier and
has higher serial clock frequency than master.(using the lowest
frequency 4 MHz)

Hooked up logic analyzer and counted the clock cycles in the programming
cycle. The slave FPGA clock count varies, both when it fails and when
it programs(manual program intiation). When it fails it is lower than
the required count but varies from one try to another. When it succeeds
it is higher than required and also vaires from one try to another.

Master FPGA clock count is always the same.

Any suggestions on what could be causing this problem?

Thanks
Brijesh
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top