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Rick C
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On Friday, September 25, 2020 at 3:16:19 PM UTC-4, John Larkin wrote:
You don\'t say how much the total delay is or what your circuitry is other than \"a fair lot of stuff\". I\'m pretty sure the FPGA makers focus on minimizing worst case delay rather than making it more even with temperature. No one would have much use for that when push comes to shove. If it works, just barely, at high temperature, what is the point of maintaining a bare timing margin at lower temps rather than letting it speed up?
It may well be that when going on and off chip the I/O delays make up the lion\'s share of the timing and they may not behave the same as the bulk since they are mostly about large structures.
Hardly. More like they focus on optimizing clock speeds so raw on chip logic and routing speed. Try using a clock in your design and see how fast it will operate. We did that once when the design software was marginal and did not properly estimate delay on a heavily loaded net. It would report meeting the clock speed requirement when it was actually failing. Cold spray would make it work. In the end we had to test using a heat plate to be able to ship a product.
What a PITA. Timing/heat problems are awkward to debug when the tools are not of much help.
Are you not cooling it enough to keep it from crashing?
--
Rick C.
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I have a time-critical thing where the signal passes through an XC7A15
FPGA and does a fair lot of stuff inside. I measured delay vs some
voltages:
1.8 aux no measurable DC effect
3.3 vccio no measurable DC effect
2.5 vccio ditto (key io\'s are LVDS in this bank)
+1 core -10 ps per millivolt!
If I vary the trigger frequency, I can see the delay heterodyning
against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track
that down.
A spritz of freeze spray on the chip had practically no effect on
delay through the chip, on a scope at 100 ps/div.
You don\'t say how much the total delay is or what your circuitry is other than \"a fair lot of stuff\". I\'m pretty sure the FPGA makers focus on minimizing worst case delay rather than making it more even with temperature. No one would have much use for that when push comes to shove. If it works, just barely, at high temperature, what is the point of maintaining a bare timing margin at lower temps rather than letting it speed up?
It may well be that when going on and off chip the I/O delays make up the lion\'s share of the timing and they may not behave the same as the bulk since they are mostly about large structures.
I expected sensitivity to core voltage, so we\'ll make sure we have a
serious, analog-quality voltage regulator next rev.
The temperature thing surprised me. I was used to CMOS having a
serious positive delay TC. Maybe modern FPGAs have some sort of
temperature compensation designed in?
Hardly. More like they focus on optimizing clock speeds so raw on chip logic and routing speed. Try using a clock in your design and see how fast it will operate. We did that once when the design software was marginal and did not properly estimate delay on a heavily loaded net. It would report meeting the clock speed requirement when it was actually failing. Cold spray would make it work. In the end we had to test using a heat plate to be able to ship a product.
We also have a ZYNQ on this board that crashes the ARM core
erratically, especially when the chip is hot. It might crash in maybe
a half hour MTBF if the chip reports 55C internally; the FPGA part
keeps going. At powerup boot from an SD card, it will always configure
the PL FPGA side, but will then fail to run our application if the
chip is hot. We\'re playing with DRAM and CPU clock rates to see if
that has much effect.
What a PITA. Timing/heat problems are awkward to debug when the tools are not of much help.
Are you not cooling it enough to keep it from crashing?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209