FPGA Selection--

G

George

Guest
I've attempting to select an FPGA for a new design.

The design will have 9 of the following:
12 bit latches
12 bit down counter
1 bit output latch

So one measure of the size might be 25 registers * 9 = 225 registers.

The counting freq is 15 MHz.

The latches get loaded from an existing micro. So I need a 12 input
pins for a data buss, 4 input pins for which register, a clock pin and
let's say 4 pins for control lines.
Along with the 9 output signals.

So another measure is 12+4+1+4+9 = 30 pins not counting power and
ground.

It would also be desirable to be packaged in a PLCC but TQFP in ok.

And the device should be reprogrammable using JTAG (add 4 more pins).

Voltage is not much of an issue. However 5 V tolerant I/O would be
nice.

I've looked at Lattice and Altera and haven't found the perfect
solution. I can use larger than necessary Altera devices (ACEX1K)
but that seems to be the wrong direction.

Any suggestions/recommendations.

Thanks
George
 
George wrote:
I've attempting to select an FPGA for a new design.

The design will have 9 of the following:
12 bit latches
12 bit down counter
1 bit output latch

So one measure of the size might be 25 registers * 9 = 225 registers.

The counting freq is 15 MHz.

The latches get loaded from an existing micro. So I need a 12 input
pins for a data buss, 4 input pins for which register, a clock pin and
let's say 4 pins for control lines.
Along with the 9 output signals.

So another measure is 12+4+1+4+9 = 30 pins not counting power and
ground.

It would also be desirable to be packaged in a PLCC but TQFP in ok.

And the device should be reprogrammable using JTAG (add 4 more pins).

Voltage is not much of an issue. However 5 V tolerant I/O would be
nice.

I've looked at Lattice and Altera and haven't found the perfect
solution. I can use larger than necessary Altera devices (ACEX1K)
but that seems to be the wrong direction.

Any suggestions/recommendations.
Click to expand...
PLCC / 5V /15MHz / 225 registers is more trailing edge, so look at
Atmel's AT40K FPGA family (meets all features), or possibly a CPLD -
Lattices 4000 family have 5V tolerant I/O ?
-jg
 
There is the XCR3256XL

http://direct.xilinx.com/bvdocs/publications/ds013.pdf

This is a 256 macrocell part that operates at 3.3V. It has
the required 225 flops (31 to spare), JTAG and is 5V tolerant
on the I/Os. It is offered in both TQ and PLCC packages.
15 MHz would bea "piece of cake". It's
overkill in the I/O , but more is
better than less.
Of course, there is a 1.8V version, but it
does note tolerate 5V without extra circuitry on the outside.

Peter Alfke, Xilinx Applications
==================================
From: george.martin@att.net (George)
Organization: http://groups.google.com
Newsgroups: comp.arch.fpga
Date: 21 Jul 2004 13:02:10 -0700
Subject: FPGA Selection--
Click to expand...
 
Jim,

Lattice's ispMACH4000 is a great family and available in different
packages. However, George mentioned he want's to use a PQFP,and the
ispMACH4000 is not available in PQFP. Ttherefore I would like to
suggest a M4A3-256/128-10YC. This is the previous generation.
If price matters, and George can live with TQPF (which is actual a
smaller package) then he can chose the LC4256V-75T100C. This device
has 64 IOs.

Regards,

Luc

On Thu, 22 Jul 2004 09:16:05 +1200, Jim Granville
<no.spam@designtools.co.nz> wrote:

George wrote:
I've attempting to select an FPGA for a new design.

The design will have 9 of the following:
12 bit latches
12 bit down counter
1 bit output latch

So one measure of the size might be 25 registers * 9 = 225 registers.

The counting freq is 15 MHz.

The latches get loaded from an existing micro. So I need a 12 input
pins for a data buss, 4 input pins for which register, a clock pin and
let's say 4 pins for control lines.
Along with the 9 output signals.

So another measure is 12+4+1+4+9 = 30 pins not counting power and
ground.

It would also be desirable to be packaged in a PLCC but TQFP in ok.

And the device should be reprogrammable using JTAG (add 4 more pins).

Voltage is not much of an issue. However 5 V tolerant I/O would be
nice.

I've looked at Lattice and Altera and haven't found the perfect
solution. I can use larger than necessary Altera devices (ACEX1K)
but that seems to be the wrong direction.

Any suggestions/recommendations.

PLCC / 5V /15MHz / 225 registers is more trailing edge, so look at
Atmel's AT40K FPGA family (meets all features), or possibly a CPLD -
Lattices 4000 family have 5V tolerant I/O ?
-jg
Click to expand...
 
"George" <george.martin@att.net> skrev i meddelandet
news:e9d879fa.0407211202.5f0f81ef@posting.google.com...
I've attempting to select an FPGA for a new design.

The design will have 9 of the following:
12 bit latches
12 bit down counter
1 bit output latch

So one measure of the size might be 25 registers * 9 = 225 registers.

The counting freq is 15 MHz.

The latches get loaded from an existing micro. So I need a 12 input
pins for a data buss, 4 input pins for which register, a clock pin and
let's say 4 pins for control lines.
Along with the 9 output signals.

So another measure is 12+4+1+4+9 = 30 pins not counting power and
ground.

It would also be desirable to be packaged in a PLCC but TQFP in ok.

And the device should be reprogrammable using JTAG (add 4 more pins).

Voltage is not much of an issue. However 5 V tolerant I/O would be
nice.

I've looked at Lattice and Altera and haven't found the perfect
solution. I can use larger than necessary Altera devices (ACEX1K)
but that seems to be the wrong direction.

Any suggestions/recommendations.
Click to expand...

Check out the AT94K10 or AT94K05.
This gives you both the (AVR) micro and the FPGA.

--
Best Regards
Ulf at atmel dot com
These comments are intended to be my own opinion and they
may, or may not be shared by my employer, Atmel Sweden.

Thanks
George
Click to expand...
 
\On Wed, 21 Jul 2004 13:02:10 -0700, George wrote:

I've attempting to select an FPGA for a new design.

The design will have 9 of the following:
12 bit latches
12 bit down counter
1 bit output latch

So one measure of the size might be 25 registers * 9 = 225 registers.

The counting freq is 15 MHz.

The latches get loaded from an existing micro. So I need a 12 input
pins for a data buss, 4 input pins for which register, a clock pin and
let's say 4 pins for control lines.
Along with the 9 output signals.

So another measure is 12+4+1+4+9 = 30 pins not counting power and
ground.

It would also be desirable to be packaged in a PLCC but TQFP in ok.

And the device should be reprogrammable using JTAG (add 4 more pins).

Voltage is not much of an issue. However 5 V tolerant I/O would be
nice.

I've looked at Lattice and Altera and haven't found the perfect
solution. I can use larger than necessary Altera devices (ACEX1K)
but that seems to be the wrong direction.

Any suggestions/recommendations.

Thanks
George
Click to expand...
You don't need an FPGA for something that simple, look at CPLDs.
 
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