FPGA pin re-configuration

C

Carl Horton

Guest
Our existing Xilinx FPGA board has some test output pins of type
IO_LXXY_#. They are now configured as IOSTANDARD = LVDS_25 and
IOSTANDARD = LVTTL. They are connected to TSW connectors.
We wanted to configure them as input pins. Is there anything that we
should pay attention on?

Where can I find the information on how to design the input and output
buffers on PCB? Thanks in advance!
 
Our existing Xilinx FPGA board has some test output pins of type
IO_LXXY_#. They are now configured as IOSTANDARD = LVDS_25 and
IOSTANDARD = LVTTL. They are connected to TSW connectors.
We wanted to configure them as input pins. Is there anything that we
should pay attention on?

Where can I find the information on how to design the input and output
buffers on PCB? Thanks in advance!
Click to expand...
I am unsure of what exactly you are asking. IO_LXXY_# gives the location o
the IO pin inside the FPGA. You have set these as LVDS and LVTTL. Th
buffers are contained in the IO block of the FPGA that you are using. Yo
need to look in the user guide at the section that gives info about the I
standards.

Jon

---------------------------------------
Posted through http://www.FPGARelated.com
 
Sorry. Let me try again to make it clearer. The existing Xilinx FPGA
board has some test *output* pins. Now we wanted to use them an
*input* pins instead of *output* pins. What does it need to be done to
make it work?
 
On Feb 4, 9:32 am, Carl Horton <carl.horto...@gmail.com> wrote:
Sorry. Let me try again to make it clearer. The existing Xilinx FPGA
board has some test *output* pins. Now we wanted to use them an
*input* pins instead of *output* pins. What does it need to be done to
make it work?
Click to expand...
Generate a new FPGA design with input buffers assigned to these pins
instead of output buffers.

Ed McGettigan
--
Xilinx Inc.
 
Carl Horton <carl.horton08@gmail.com> wrote:

Sorry. Let me try again to make it clearer. The existing Xilinx FPGA
board has some test *output* pins. Now we wanted to use them an
*input* pins instead of *output* pins. What does it need to be done to
make it work?
Click to expand...
If there are external (to the FPGA) unidirectional buffers, then
you have to change those. Otherwise, just change the IOB configuration
from output to input.

-- glen
 
Thanks Glen,

Some of FPGA output pins are just directly connecting to the
connector. With this, I guess we can just change the IOB configuration
to input to feed the input signal to the connector, right?

Some of FPGA output pins are going through SN75LVDS387 HIGH-SPEED
DIFFERENTIAL LINE DRIVERS and then connected to the connector. Is
SN75LVDS387 unidirectional? I guess it is, right? We have no way to
use them as input pins if we do not replace the unidirectional driver,
right?

I am not a board designer, therefore I have these questions. Thanks
for your kind help!
 
On Feb 4, 6:35 pm, Carl Horton <carl.horto...@gmail.com> wrote:
Thanks Glen,

Some of FPGA output pins are just directly connecting to the
connector. With this, I guess we can just change the IOB configuration
to input to feed the input signal to the connector, right?

Some of FPGA output pins are going through SN75LVDS387 HIGH-SPEED
DIFFERENTIAL LINE DRIVERS and then connected to the connector. Is
SN75LVDS387 unidirectional? I guess it is, right? We have no way to
use them as input pins if we do not replace the unidirectional driver,
right?

I am not a board designer, therefore I have these questions. Thanks
for your kind help!
Click to expand...
See: http://focus.ti.com/lit/ds/symlink/sn75lvds386.pdf

The SN75LVDS387 is a 16-bit LVDS driver. If you want to change the
direction of all 16 signals, then you might be in luck. If you remove
the 75LVDS387 and replace it with an SN75LVDS386 or SN75LVDT386
chip rotated 180 degrees so that pin 1 goes to the board pad for
pin 33, then all 16 bits become inputs. The LVDS pins, LVCMOS pins,
Enable pins, Vcc, and GND all line up properly in this orientation.
Check out the first page of the datasheets on TI.com to see how
the pins line up. I've done this sort of thing on Channel-Link parts
as well, which required chips to be upside-down rather than rotated.
The 'LVDT part has integrated terminating resistors, which are
probably
right for you if the board was designed for transmitter only, and
therefore has no board-level termination.

If all you want is LVCMOS I/O at the connector, then you could just
remove
the existing chip and wire across. If you need only one or two lines
to change direction you can always lift pins and wire around the chip.
Whether you rework or re-spin the boards will depend on how many
boards you need and whether the rework is acceptable in the
end use.

HTH,
Gabor
 
On Feb 4, 7:19 pm, Gabor <ga...@alacron.com> wrote:
On Feb 4, 6:35 pm, Carl Horton <carl.horto...@gmail.com> wrote:

Thanks Glen,

Some of FPGA output pins are just directly connecting to the
connector. With this, I guess we can just change the IOB configuration
to input to feed the input signal to the connector, right?

Some of FPGA output pins are going through SN75LVDS387 HIGH-SPEED
DIFFERENTIAL LINE DRIVERS and then connected to the connector. Is
SN75LVDS387 unidirectional? I guess it is, right? We have no way to
use them as input pins if we do not replace the unidirectional driver,
right?

I am not a board designer, therefore I have these questions. Thanks
for your kind help!

See:http://focus.ti.com/lit/ds/symlink/sn75lvds386.pdf

The SN75LVDS387 is a 16-bit LVDS driver.  If you want to change the
direction of all 16 signals, then you might be in luck.  If you remove
the 75LVDS387 and replace it with an SN75LVDS386 or SN75LVDT386
chip rotated 180 degrees so that pin 1 goes to the board pad for
pin 33, then all 16 bits become inputs.  The LVDS pins, LVCMOS pins,
Enable pins, Vcc, and GND all line up properly in this orientation.
Check out the first page of the datasheets on TI.com to see how
the pins line up.  I've done this sort of thing on Channel-Link parts
as well, which required chips to be upside-down rather than rotated.
Click to expand...
Dang! That is amazing. But for some reason, they didn't design the 8
and 4 bit versions of the chip for the same trick. I guess it was
just lucky coincidence driven by a commonality in internal layout.

One limitation is that while this will get the inputs and outputs on
the right sets of pins, the polarity of the inputs and outputs are
reversed, so if this is part of a system cabling might have to
change. 1 to 1 cabling won't connect up correctly... but that is just
a polarity issue and may be correctable in software or some other
place.

Rick
 
On Feb 4, 10:00 pm, rickman <gnu...@gmail.com> wrote:
[snip]
Dang!  That is amazing.  But for some reason, they didn't design the 8
and 4 bit versions of the chip for the same trick.  I guess it was
just lucky coincidence driven by a commonality in internal layout.

One limitation is that while this will get the inputs and outputs on
the right sets of pins, the polarity of the inputs and outputs are
reversed, so if this is part of a system cabling might have to
change.  1 to 1 cabling won't connect up correctly... but that is just
a polarity issue and may be correctable in software or some other
place.

Rick
Click to expand...
O.K. I assume that since the FPGA code was changing the inversion
could happen inside the FPGA, but if you really want to stick with
non-inverted signals, then flip the chip on its back instead of
rotating
it. As I said before we do that with Channel Link chips, but
generally
speaking rotating the part is easier than flipping it over because you
don't need to re-form the leads.

-- Gabor
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top