FPGA not getting programmed

S

salimbaba

Guest
Hi,
I am using a custom board design in which i have 2 FPGAs (spartan
xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is lik
this:

EEPROM -> FPGA1 -> FPGA2

Now the problem is that when i try to program the FPGA using JTAG, my DON
goes high, INIT_B stays high and PROG_B stays high after config, iMPAC
says program succeeded but FPGA doesn't work. If i run chipscope, it says
cores found.
Same goes when i try to program FPGAs using EEPROM. I have tried in dais
chain and even programming the FPGAs individually by disconnecting the
from the chain.

Now there's another dynamic to this problem, i have a previously built .bi
file, when i program the FPGAs using it, they get programmed. But if i tr
to program the FPGAs with any other .bit file, they don't. I am clueles
now and i cannot find the problem.

I need help here..

Thanks
regards


---------------------------------------
Posted through http://www.FPGARelated.com
 
Hi,
I am using a custom board design in which i have 2 FPGAs (spartan 3
xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like
this:

EEPROM -> FPGA1 -> FPGA2
Click to expand...
unless the 2 FPGAs are identical, the first problem I can see here is
that XCF16P (16 MBit) is not big enough to store the configuration
bits for both FPGAs (11,316,864bits) .. see page 86 of UG332
 
Hi,
I am using a custom board design in which i have 2 FPGAs (spartan 3
xc3s4000) and an EEPROM xcf16p daisy chained together. The chain i
like
this:

EEPROM -> FPGA1 -> FPGA2

unless the 2 FPGAs are identical, the first problem I can see here is
that XCF16P (16 MBit) is not big enough to store the configuration
bits for both FPGAs (11,316,864bits) .. see page 86 of UG332
Click to expand...

The FPGAs are identical and i am trying to configure only one FPGA at th
moment using JTAG. So, EEPROM signals can be ignored for now.

---------------------------------------
Posted through http://www.FPGARelated.com
 
As you have a bit file that does work, could it be a pin constraint
problem? (worng UCF file, no ucf file...)
could it be that the bit file you are using is not actually the file
you intended to use? (impact pickin up the bit file from an other
folder?)
 
On Jul 14, 8:45 pm, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Hi,
I am using a custom board design in which i have 2 FPGAs (spartan 3
xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is like
this:

EEPROM -> FPGA1 -> FPGA2

Now the problem is that when i try to program the FPGA using JTAG, my DONE
goes high, INIT_B stays high and PROG_B stays high after config, iMPACT
says program succeeded but FPGA doesn't work. If i run chipscope, it says 0
cores found.
Same goes when i try to program FPGAs using EEPROM. I have tried in daisy
chain and even programming the FPGAs individually by disconnecting them
from the chain.

Now there's another dynamic to this problem, i have a previously built .bit
file, when i program the FPGAs using it, they get programmed. But if i try
to program the FPGAs with any other .bit file, they don't. I am clueless
now and i cannot find the problem.

I need help here..

Thanks
regards

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
Had this problem about four years ago.
From memory, done is connected to both FPGAs with a single pull up. If
you program one device using JTAG it lets go of done but the other
unprogrammed device still pulls done low and config says that it has
failed.

Program FPGA A. A lets go of done but B still pulls it low and the
final bit of jtag says that it has failed (done is still low).
Program FPGA B. B lets go of done which can now go high and B is
configured correctly.
Now program A again and it drives done low, configures, lets go of
done and now knows that it has configured correctly.

Colin
 
On Jul 14, 8:45=A0pm, "salimbaba"
a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Hi,
I am using a custom board design in which i have 2 FPGAs (spartan 3
xc3s4000) and an EEPROM xcf16p daisy chained together. The chain i
like
this:

EEPROM -> FPGA1 -> FPGA2

Now the problem is that when i try to program the FPGA using JTAG, m
DON=
E
goes high, INIT_B stays high and PROG_B stays high after config, iMPACT
says program succeeded but FPGA doesn't work. If i run chipscope, i
says=
0
cores found.
Same goes when i try to program FPGAs using EEPROM. I have tried i
daisy
chain and even programming the FPGAs individually by disconnecting them
from the chain.

Now there's another dynamic to this problem, i have a previously buil
.b=
it
file, when i program the FPGAs using it, they get programmed. But if
tr=
y
to program the FPGAs with any other .bit file, they don't. I a
clueless
now and i cannot find the problem.

I need help here..

Thanks
regards

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Had this problem about four years ago.
From memory, done is connected to both FPGAs with a single pull up. If
you program one device using JTAG it lets go of done but the other
unprogrammed device still pulls done low and config says that it has
failed.

Program FPGA A. A lets go of done but B still pulls it low and the
final bit of jtag says that it has failed (done is still low).
Program FPGA B. B lets go of done which can now go high and B is
configured correctly.
Now program A again and it drives done low, configures, lets go of
done and now knows that it has configured correctly.

Colin
Click to expand...
Colin,
i have already done that, no success. On some .bit files it get
programmed,otherwise it doesn't. I saw in FPGA editor that xilinx XS
sometimes maps my signals on to INIT_B pad, was wondering if it coul
create problems. I am not mapping any signal on the INIT_B pad, xilinx map
it i don't know why.
---------------------------------------
Posted through http://www.FPGARelated.com
 
Which signal is being mapped on to the INIT_B pad? And where did you
constrain this signal to be LOC'ed to?

You are using LOC constraints on all of your I/O right?

Ed McGettigan
--
Xilinx Inc.
Click to expand...

It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am no
using LOC constraints on all the IOs ..

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Jul 18, 7:08 am, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
On Jul 14, 8:45=A0pm, "salimbaba"
a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Hi,
I am using a custom board design in which i have 2 FPGAs (spartan 3
xc3s4000) and an EEPROM xcf16p daisy chained together. The chain is
like
this:

EEPROM -> FPGA1 -> FPGA2

Now the problem is that when i try to program the FPGA using JTAG, my
DON> >E
goes high, INIT_B stays high and PROG_B stays high after config, iMPACT
says program succeeded but FPGA doesn't work. If i run chipscope, it
says> > 0
cores found.
Same goes when i try to program FPGAs using EEPROM. I have tried in
daisy
chain and even programming the FPGAs individually by disconnecting them
from the chain.

Now there's another dynamic to this problem, i have a previously built
.b> >it
file, when i program the FPGAs using it, they get programmed. But if i
tr> >y
to program the FPGAs with any other .bit file, they don't. I am
clueless
now and i cannot find the problem.

I need help here..

Thanks
regards

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Had this problem about four years ago.
From memory, done is connected to both FPGAs with a single pull up. If
you program one device using JTAG it lets go of done but the other
unprogrammed device still pulls done low and config says that it has
failed.

Program FPGA A. A lets go of done but B still pulls it low and the
final bit of jtag says that it has failed (done is still low).
Program FPGA B. B lets go of done which can now go high and B is
configured correctly.
Now program A again and it drives done low, configures, lets go of
done and now knows that it has configured correctly.

Colin

Colin,
i have already done that, no success. On some .bit files it gets
programmed,otherwise it doesn't. I saw in FPGA editor that xilinx XST
sometimes maps my signals on to INIT_B pad, was wondering if it could
create problems. I am not mapping any signal on the INIT_B pad, xilinx maps
it i don't know why.



---------------------------------------        
Posted throughhttp://www.FPGARelated.com- Hide quoted text -

- Show quoted text -
Click to expand...
Which signal is being mapped on to the INIT_B pad? And where did you
constrain this signal to be LOC'ed to?

You are using LOC constraints on all of your I/O right?

Ed McGettigan
--
Xilinx Inc.
 
On Jul 18, 8:32 am, "salimbaba"
<a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Which signal is being mapped on to the INIT_B pad?  And where did you
constrain this signal to be LOC'ed to?

You are using LOC constraints on all of your I/O right?

Ed McGettigan
--
Xilinx Inc.

It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am not
using LOC constraints on all the IOs ..    

---------------------------------------        
Posted throughhttp://www.FPGARelated.com
Click to expand...
Creating a design to be downloaded into a board without fully LOC
constraining all of the IO is just asking for trouble and can
potentially damage the FPGA or another device on the board.

You need to fix this ASAP and it will very likely resolve your
original problem.

Ed McGettigan
--
Xilinx Inc.
 
On Jul 18, 8:32=A0am, "salimbaba"
a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Which signal is being mapped on to the INIT_B pad? =A0And where di
you
constrain this signal to be LOC'ed to?

You are using LOC constraints on all of your I/O right?

Ed McGettigan
--
Xilinx Inc.

It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i a
n=
ot
using LOC constraints on all the IOs .. =A0 =A0

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Creating a design to be downloaded into a board without fully LOC
constraining all of the IO is just asking for trouble and can
potentially damage the FPGA or another device on the board.

You need to fix this ASAP and it will very likely resolve your
original problem.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
okay i'll fix it and then update you.
Thanks

Regards


---------------------------------------
Posted through http://www.FPGARelated.com
 
On Jul 19, 3:20 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Jul 18, 8:32 am, "salimbaba"

a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Which signal is being mapped on to the INIT_B pad?  And where did you
constrain this signal to be LOC'ed to?

You are using LOC constraints on all of your I/O right?

Ed McGettigan
--
Xilinx Inc.

It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am not
using LOC constraints on all the IOs ..    

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Creating a design to be downloaded into a board without fully LOC
constraining all of the IO is just asking for trouble and can
potentially damage the FPGA or another device on the board.

You need to fix this ASAP and it will very likely resolve your
original problem.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
Ed's point is very much valid. You should fully Constrain all the IO
signals in your design before you start implementation. I have faced
this problem long back. Every board has specific pins for JTAG
interface, but if you don't constrain your IOBs, it may end up in
using these JTAG specific IO's by your normal logic IO signals.

-- vasu
 
On Jul 19, 12:54 am, vasu <vasu.devun...@gmail.com> wrote:
On Jul 19, 3:20 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Jul 18, 8:32 am, "salimbaba"

a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Which signal is being mapped on to the INIT_B pad?  And where did you
constrain this signal to be LOC'ed to?

You are using LOC constraints on all of your I/O right?

Ed McGettigan
--
Xilinx Inc.

It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am not
using LOC constraints on all the IOs ..    

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Creating a design to be downloaded into a board without fully LOC
constraining all of the IO is just asking for trouble and can
potentially damage the FPGA or another device on the board.

You need to fix this ASAP and it will very likely resolve your
original problem.

Ed McGettigan
--
Xilinx Inc.

Ed's point is very much valid. You should fully Constrain all the IO
signals in your design  before you start implementation. I have faced
this problem long back. Every board has specific pins for JTAG
interface, but if you don't constrain your IOBs, it may end up in
using these JTAG specific IO's by your normal logic IO signals.

-- vasu- Hide quoted text -

- Show quoted text -
Click to expand...
Some older FPGA families did not use dedicated JTAG pins, but all
modern FPGAs do have dedicated JTAG pins.

Ed McGettigan
--
Xilinx Inc.
 
On Jul 20, 5:19 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
On Jul 19, 12:54 am, vasu <vasu.devun...@gmail.com> wrote:









On Jul 19, 3:20 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:

On Jul 18, 8:32 am, "salimbaba"

a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote:
Which signal is being mapped on to the INIT_B pad?  And where did you
constrain this signal to be LOC'ed to?

You are using LOC constraints on all of your I/O right?

Ed McGettigan
--
Xilinx Inc.

It is an IO which i didnt LOC'ed so INIT_B was mapped on to it.And i am not
using LOC constraints on all the IOs ..    

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Creating a design to be downloaded into a board without fully LOC
constraining all of the IO is just asking for trouble and can
potentially damage the FPGA or another device on the board.

You need to fix this ASAP and it will very likely resolve your
original problem.

Ed McGettigan
--
Xilinx Inc.

Ed's point is very much valid. You should fully Constrain all the IO
signals in your design  before you start implementation. I have faced
this problem long back. Every board has specific pins for JTAG
interface, but if you don't constrain your IOBs, it may end up in
using these JTAG specific IO's by your normal logic IO signals.

-- vasu- Hide quoted text -

- Show quoted text -

Some older FPGA families did not use dedicated JTAG pins, but all
modern FPGAs do have dedicated JTAG pins.

Ed McGettigan
--
Xilinx Inc.
Click to expand...
I faced this problem in Virtex-6 FPGA based design.
 
"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message
news:1b9eb6a7-70d2-44fa-9710-0c2eb22262db@t8g2000prm.googlegroups.com...
Some older FPGA families did not use dedicated JTAG pins, but all
modern FPGAs do have dedicated JTAG pins.
Click to expand...
I guess modern FPGA's have just sw dedicated jtag pins.. At least Altera's
can be used as IO through megafunctions (like sld_virtual_jtag). I agree
that's the way to do it instead of letting them loose as generic io.
 
I am wondering if have two FPGAs being programmed from the same EEPROM is even a valid JTAG structure? Someone please correct if I am incorrect and has designed a working system this way before. I would almost lean towards having the JTAG chain only be

EEPROM -> FPGA1

Then have FPGA1 read the bit stream out of EEPROM and program FPGA2. Therefore you don't have bus contention between the two FPGAs. FPGA2 is then like a ghost FPGA on the JTAG chain.

Does this seem logical? I have just never heard of one EEPROM being dedicated to two FPGAs before with identical bit files.
 
Dustin Brothers wrote:
I am wondering if have two FPGAs being programmed from the same EEPROM is even a valid JTAG structure? Someone please correct if I am incorrect and has designed a working system this way before. I would almost lean towards having the JTAG chain only be

EEPROM -> FPGA1

Then have FPGA1 read the bit stream out of EEPROM and program FPGA2. Therefore you don't have bus contention between the two FPGAs. FPGA2 is then like a ghost FPGA on the JTAG chain.

Does this seem logical? I have just never heard of one EEPROM being dedicated to two FPGAs before with identical bit files.
Click to expand...
Actually it is quite common to use a single PROM or flash to program
multiple FPGA's. This connection scheme is shown in the Spartan 3
Generation Configuration User Guide.

From the other posts in the thread, it seems more likely to be a
problem with bit file generation rather than the board-level
connections.

-- Gabor
 
Gabor,

Ok awesome, thanks for the clarity. I have never designed a system in this configuration which is why I was asking :)

-D
 
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